Highest Voted 'rocket-chip' Questions

1

vote

0 answers

How to ristrict Slave port's visiliblity when creating new AXI4 Slave port?

I want to create an AXI4Slave port using CanHaveSlaveAXI4Port and CanHaveSlaveAXI4PortModuleImp. I was successfully able to create those. But now I want to restrict the port so it can only access the defined memory region. I know I can do that when…

chisel rocket-chip

asked Feb 27 '20 at 19:08

hitoswal

11
2

1

vote

1 answer

32 bit hella cache access for coprocessor acculator example

I've implemented 32 bit rocket chip with rocc example, but in accumulator example while accessing data through hella cache interface using do_load instruction. The io_mem_response_valid signal remains high for two clock cycle so data in reg file is…

riscv rocket-chip

asked Jan 14 '20 at 06:08

Sanket Khandare

83
6

1

vote

2 answers

How is this syntax explained in chisel?

I am learning chisel and rocket-chip. I recently found an unreadable syntax in the rocket / RocketCore.scala file. val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(mask(0), wb_xcpt, wb_valid && pipelineIDToWB((mask & hits).orR)),…

scala chisel rocket-chip

asked Dec 17 '19 at 13:26

Self-Motivated Wu

397
2
9

1

vote

1 answer

How to keep val names under withClock() or withClockAndReset() scopes

Val names under withClock() & withClockAndReset() scopes tend to lose their coded names in the generated Verilog file. So far in order to maintain to original names I used suggestName() function to force the original name. However I wonder if there…

chisel rocket-chip

asked Dec 05 '19 at 06:02

user3567895

618
3
14

1

vote

0 answers

Loading and Storing into L1 cache of Rocket Chip

I have an accelerator attached to my RISC V core and until now I was sending data through the RoCC interface. Now I want to send and receive the data through the L1 cache. I know mem field connects to the cache but how exactly do we perform load and…

chisel rocket-chip

asked Nov 14 '19 at 00:19

CV_Ruddha

406
2
13

1

vote

3 answers

Is it possible to implement the current Rocket Chip Github respo on FPGAs other than Artix-7

I am totally new to the RISC-V domain. I am targeting to implement the Rocket Chip core on my FPGA as a module of a bigger project. As far as I know, SiFive is a supplier for the Rocket Chip. To my knowledge, SiFive makes all its cores implementable…

fpga riscv rocket-chip

asked Nov 04 '19 at 12:06

Abdelrahman Hussein

31
3

1

vote

1 answer

Getting a SimpleHellaCacheIF exception when making two memory accesses from the same instruction

I am trying to modify the accumulator generator example to load two accesses at once, for example to load two indices from one array. All I changed is that when the first memory response comes in, I increment a counter and send out another. But I…

memory riscv chisel rocket-chip

asked Oct 31 '19 at 13:12

user7554160

25
3

1

vote

2 answers

How can I find some manuals about rocket-chip?

I'm learning the code of rocket-chip. But I find it difficult to read its code due to the complex relationship. So I need some maunal to help me. Unluckily, it seems that there are few manuals about it. So could anyone provide me with manuals which…

riscv chisel rocket-chip

asked Jun 07 '19 at 12:42

lovezjt

43
3

1

vote

1 answer

What is the purpose of the makeSink method in making IOs for a periphery

I was following some examples of adding peripheries to the rocketchip. I used the sifive-blocks as reference. below is an example from their I2C example (I hope it's ok to post it here) case object PeripheryI2CKey extends…

chisel rocket-chip

asked Jun 03 '19 at 01:09

user3567895

618
3
14

1

vote

1 answer

declaration and Variable scope in chisel and When block

so I am adding when block around a line in the code but the problem is adding this when block changes the scope making the variables declared inside it not seen from other parts in the program The problem is that in cases like that val (_, _,…

chisel rocket-chip

asked Jun 02 '19 at 12:32

Ahmed Salman

13
2

1

vote

0 answers

How to enable virtual memory for bare metal benchmarks on Rocket-chip?

We are testing virtual memory hardware in rocket chip, and want to run test applications bare metal. In the Rocket Chip test harness, there are a number of toy benchmarks that run bare metal, but they don’t enable virtual memory. There are a few…

riscv rocket-chip

asked May 25 '19 at 19:36

Lbs

11
2

1

vote

0 answers

Installing rocket chip generator

I've been trying to install rocket-chip generator. This is what I have done $ git clone https://github.com/ucb-bar/rocket-chip.git $ cd rocket-chip $ export ROCKETCHIP='pwd' $ git submodule update --init $ export RISCV=/home/user1/rocket-chip and…

riscv rocket-chip

asked Mar 15 '19 at 03:30

full_adder0

31
3

1

vote

0 answers

How does scratchpad works in rocketcore icache?

It is confusing to me the role of scratchpad in icache in the rocket core. Could anyone help explain it?

architecture riscv chisel rocket-chip

asked Nov 30 '18 at 02:20

Shibo Chen

77
6

1

vote

1 answer

what is "wxd" in rocketcore?

In the rocket core bypass logic val bypass_sources = IndexedSeq( (Bool(true), UInt(0), UInt(0)), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr,…

riscv chisel rocket-chip

asked Nov 15 '18 at 19:52

Shibo Chen

77
6

1

vote

2 answers

What do the (site, here, up) arguments mean when creating rocket-chip configurations?

When creating a new "Config" we define a function that takes three "View"s (site, here, up) as arguments. What is the meaning of these three Views?

chisel rocket-chip

asked Nov 10 '18 at 20:06

Ben Reynwar

1,547
14
21

Questions tagged [rocket-chip]