Highest Voted 'rocket-chip' Questions

2

votes

2 answers

sbt could not find implicit value for parameter valName

I'm using sbt to build some of the riscv boom from the source code, but the sbt complains that it "could not find implicit value for parameter valName: : freechips.rocketchip.diplomacy.ValName". The detailed error message are as below: [error]…

asked Jul 26 '19 at 01:52

qqyang10110

21
1

2

votes

0 answers

Is there any open source tilelink verification infrastructure?

We are building a TileLink protocol convertor which involves setting up a verification environment that generates and records sequences of TileLink messages. We're wondering if there's any existing TileLink verification collateral we can leverage?…

riscv chisel rocket-chip

asked Jul 19 '19 at 18:45

lenny

21
1
2

2

votes

2 answers

comparing the value in a register to an int

I am trying to get the value of a reg and compare it with a number inside and if statement val refill_addr = Reg(UInt(width = paddrBits)) if ( refill_addr > 20000.U) cacheable := true else cacheable := false but i get this…

chisel rocket-chip

asked May 27 '19 at 16:50

A_S

45
1
5

2

votes

0 answers

How to access a sub module register from TestHarness?

I want to change value stored in a rocket core register from the test bench TestHarness.scala. How can I access the register? In TestHarness.scala, I think dut is used to instantiate the ExampleRocketSystem module: val dut = Module(LazyModule(new…

riscv chisel rocket-chip

asked May 02 '19 at 16:02

Bing

21
1

2

votes

2 answers

Any way to work around JVM code size limits tripped by large Chisel file

Just say you were autogenerating some Chisel code for some infrastructure in your chip. A single file instantiating a load of memory mapped registers and then IO assignments. Then say one day you add an extra register and the JVM goes bang and…

scala jvm chisel rocket-chip

asked Nov 27 '18 at 02:48

jbaxter

182
10

2

votes

1 answer

Rebased and now facing Scala dependency issues

I'm not quite sure where I was with the rocket-chip repo before the rebase, but it was prior to the changeover to using Scala 2.12.4 (previously I was at 2.11.12). I've rebased, sorted out conflicts in a couple of Chisel files and ran a git…

scala chisel rocket-chip

asked Aug 28 '18 at 03:01

jbaxter

182
10

2

votes

1 answer

Rocket-chip instruction trace columns

When I run make run-asm-tests in the emulator directory of rocket-chip, I get a bunch of *.out files in the emulator/output directory. These appear to be instruction traces but the columns are not labeled. I was wondering what each of these columns…

riscv rocket-chip

asked Jul 18 '18 at 20:18

Jack Koenig

5,840
15
21

2

votes

0 answers

How to monitor performance of rocket core?

In rocket/RocketCore.scala There exists performance counter which describes cache misses, load, or store. How can I see this information after rocket core finishes its running? Could you give me an example on how to do this? As far as I know,…

riscv rocket-chip

asked Jun 20 '18 at 09:09

sungjun cho

809
7
18

2

votes

1 answer

Rocket chip simulation shows unexpected instruction count

The following two code snippets differ only the value loaded into the x23 register, but the minstret instruction counts (reported by a Verilator simulation of the Rocket chip) differ substantially. Is this a bug, or am I doing something wrong? The…

riscv chisel verilator rocket-chip

asked Jun 13 '18 at 22:56

radiosonde

31
6

2

votes

1 answer

Rocketchip (riscv) acclerator performance evaluation

I have implemented accelerator on Rocket chip generator using Rocc. How to compute the performance of accelerator and compare with C implementation. I have written C implementation and computing the cycles as "Cycle = End - Begin". Where end and…

riscv chisel rocket-chip

asked May 13 '18 at 14:12

ARK91

373
3
13

2

votes

1 answer

Configuring Rocket Chip

I want to build my own SOC based on the rocket chip without the use a ROCC(arm coprocessor). I checked this useful question: rocket chip on non zynq FPGA I looked for some detailed documentation but I only found few slides describing the…

fpga riscv rocket-chip

asked Mar 19 '18 at 13:40

Ryan

45
9

1

vote

1 answer

using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language

I want to use rocket chip to generate a axi4crossbar with 2 slave ports and 1 master port, here is my chisel source code package empty import chipsalliance.rocketchip.config.{Config, Parameters} import chisel3._ import…

chisel rocket-chip axi4

asked Mar 21 '23 at 03:34

xlgforever

21
3

1

vote

0 answers

Documentation for RocketChip-generator

I recently started digging into the rocketchip generator because I want to use it for a project. I am really new to chisel and the way that RocketChip is generated. By now i figured out how I can configure a rocketchip and how I simulate the scala…

rocket-chip

asked Mar 09 '23 at 10:11

User4711

11
1

1

vote

1 answer

Scala syntax question in Rocket-chip config.scala

I just learned about the scalar to study rocket chips. I see some strange codes in the Config.scala of Rocket-chip abstract class Field[T] private (val default: Option[T]) { def this() // 1st-this = this(None) // 2nd-this def…

scala chisel rocket-chip

asked Nov 29 '22 at 20:58

astrohan

56
7

1

vote

0 answers

How to run multi-thread programs in rocket-chip?

I am trying to run multi-thread programs/benchmark in a rocket-chip SoC I generated from chipyard. I generated the TutorialConfig SoC given in https://fires.im/isca22-slides-pdf/03_building_custom_socs.pdf, which consists of a Rocket core and a BOOM…

multithreading riscv rocket-chip

asked Oct 19 '22 at 19:20

sammy17

35
5

Questions tagged [rocket-chip]