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Questions tagged [rocket-chip]

Use for questions related to the Rocket-Chip SoC generator, used to generate and simulate multi-core RISC-V-based SOCs.

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129 questions
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Implementing a diplomatic AXI Stream interface in Chisel - BundleMap.cloneType error

I am trying to build a minimal example, of how to generate an AXI4Stream interface using Chisel and diplomacy. I am using the diplomatic interface already available in rocket-chip (freechips.rocketchip.amba.axis). I have some experience with Chisel,…
Jure Vreča
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Developing Generic AXI4 Peripheral with Chisel

I want to develop a generic AXI4 peripheral with Chisel. Can I use the Rocket-Chip's AMBA library for this purpose? I could only find the document in the link below on this subject; MMIO-Peripherals However, the example in this document is designed…
overlord
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chisel Vec() in Bundle class cannot be implemented in Module class

The chisel version I'm using is 3.2.2. When I try to create a Vec of member in a Bundle class, code is like, class myIOBundle extends GenericParameterizedBundle { val en = Vec(4, Output(Bool())) val aa = Input(Vec(4, Bool())) // Used in…
hhhhy
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In chisel, How to generate serval Module with different parameter?

I have a Module monit which has an parameter threshold , then I want to generate serval(e.g.8) Module monit in the wrapper with different threshold . But when I use val monits = Seq.fill(8)(Module(new monit(32))) to create 8 modules monit, they all…
hanmeng
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option method of boolean Scala / Chisel

I was trying to understand the implementation of the AsyncQueue in the RocketChip , and quite puzzled by the use of option method on Boolean data type (not Option). In the code we have a parametr class : case class AsyncQueueParams( depth: Int …
user3567895
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Increasing AsIDBits from zero

I would like to increase the number of AsIDBits in the Rocket-Chip from zero to eight and was wondering how that could be accomplished. tile/BaseTile.Scala trait HasNonDiplomaticTileParameters { implicit val p: Parameters //... def…
Christopher Baldwin
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Accessing regmap RegFields

I am trying to find a clean way to access the regmap that is used with *RegisterNode for creating documentation and testing files. The TLRegisterNode has methods for generating the json through some Annotations. These are done in the regmap method…
l Steveo l
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Extending Data Types or way to add information

It appears that most/all of the Data types in Chisel are sealed classes which do not allow a user to extend from them. Is it possible to add information regarding some user defined fields or to add support in the future? I think there are a few…
l Steveo l
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What is the best way to debug rocke-chip chisel code?

My question is about how to actually understand and modify rocket-chip code. Reading the documentation, it seems to me that running the emulator with +verbose flag to enable prinf is the recommended way. I am not sure about the effectiveness of…
Felipe Barbosa
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Running OpenOCD fails with jtagRocketConfig

This is what I get when I try to connect Software RTL simulation and OpenOCD: xPack OpenOCD, x86_64 Open On-Chip Debugger 0.10.0+dev-00068-ge1e63ef30 (2020-03-16-05:57) Licensed under GNU GPL v2 For bug reports, read …
yildizabdullah
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What does this Chisel exception mean: Caused by: chisel3.package$RebindingException: Attempted reassignment of binding to Reset

I got the error chisel3.package$RebindingException: Attempted reassignment of binding to Reset(IO in unelaborated TLDebugModule) when attempting to change the module (TLDebugModule) from a regular Module to a RawModule. I'm not sure what this…
user839768
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How to generate a random Scala Int in Chisel code?

I am trying to implement the way-prediction technique in the RocketChip core (in-order). For this, I need to access each way separately. So this is how SRAM for tags looks like after modification (separate SRAM for each way) val tag_arrays =…
Khakim Akhunov
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Question regarding lazy evaluation for Diplomacy (rocket-chip)?

I have been reading through the Diplomacy model for Chisel. I had a question regarding the design philosophy behind this. As I can understand, the lazy evaluation of Scala is used to register some compile time information which can be forced to…
Anmol Sahoo
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Set-associative TLB on Rocket Chip

I am trying to address if Rocket Chip Generator supports a set-associative TLB (both for L1 and L2 TLB) but I cannot find any straightforward code about that in RocketCore.scala or PTW.scala. On the other hand changing the associativity of the…
ncppd
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Why traps Rocket Chip on FPGA after code execution in DRAM

I try to get a version of Rocket Chip on a Nexys4 DDR board up and running. So far I managed to generate the verilog, synthesize the design and attach a jtag probe (segger jlink). It is possible to access registers and memory via openocd and gdb.…
mdxg
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