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I tried using Mem(1024,UInt(width=xLen)); but after synthesizing generated verilog file in Xilinx vivado.The memory mapped as distributed ram. It's really tough to understand and edit generated RTL file. Is there any explicit way to define memory which can inferred as block ram.?

Thanks & Regards,

Sanket Khandare
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It looks like chisel is optimizing away the memory. Try using DontTouch construct if you want the Memory as a single unit DontTouch. Another solution is to use a wrapper around Mem. Create a Module around the Mem and then use DontTouch construct so that it remains as a single unit. And are you sure you want to use Mem construct? Mem is Asynchronous , if you want Synchronous Memory use SyncReadMem Chisel construct. Also check your Verilog file before and after synthesizing maybe Chisel isn't the culprit here. Check if Xilinx Vivado isn't optimizing it away.

CV_Ruddha
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  • hi thanks for reply, I didn't know that Mem is asynchronous. I want to infer synchronous memory, but while using SyncMem i got following error `: not found: value SyncMem`. Please assist. – Sanket Khandare Nov 03 '20 at 04:21
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    It is SyncReadMem check this link https://github.com/freechipsproject/chisel3/wiki/Memories – CV_Ruddha Nov 03 '20 at 19:11
  • Hi i resolved the problem. There was issue with design. I was trying to read synchronously but there was possibly read/write operations called for more than two times in single instance (i'm possibly trying to implement three port ram). Logically this kind of implementation can't be possible from Block Ram.So there is no issues in chisel/Vivado. I changed overall design for resolution. Even though chisel is high level language, hardware implementation remains same as verilog. – Sanket Khandare Nov 09 '20 at 08:42