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Questions tagged [verilator]

Verilator is a translation tool which converts a subset of Verilog as well as portions of SystemVerilog into C++ or SystemC.

Verilator can be used to enable test-bench development directly in C++ (including SystemC). The supported Verilog code is mostly limited to the synthesis subset, but also includes some support for features of SystemVerilog (such as interface and assert).

Verilator is licensed under the GNU Lesser Public License Version 3.

See also: Wikipedia

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How to know which simulator is used in cocotb testbench?

To test my Verilog design I'm using two differents simulators : Icarus and Verilator. It's work, but there are some variations between them. For example, I can't read module parameter with verilator, but Icarus works. Is there a way to know which…
FabienM
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Reading array of regs using Verilator and VPI

So I have the following register defined in my verilog reg [31:0] register_mem [0:15]/* verilator public */; My goal is from my verilator c++ code to read each of the 16 values stored in it. I have found that the documentation for this VPI stuff is…
J.Doe
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chisel printf fail (built using chisel3 then verilator to C++)

This is a slightly modified version of the HelloWorld.scala example from https://github.com/freechipsproject/chisel3/wiki/Frequently-Asked-Questions // say hello package…
Daniel
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Chisel randomly initialize register value when simulating with verilator

I'm using Chisel and blackbox to run my chisel logic against a verilog register file. The registerfile does not have reset signal so I expect the register to be randomly initialized. I passed the --x-initial unique to verilator, Basically this is…
Hoohoo
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What API to use for a Verilator test harness?

Verilator can output SystemC or C++ classes. There is a 'Verilator' API and I can find the headers, but they are just raw classes with no documentation. Some code looks like classes that are used directly by the backend to achieve the simulation…
artless noise
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Why is a c++ method which is defined static in a header file not showing up in a symbol table

I am trying to compile and link the runtime support code for Verilator (veripool.org). It builds fine, but for some reason there are a couple of methods which aren't showing up in the pertinent object file, Verilated::timeunit(int) and…
Jon Taylor
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How to fix chisel test errors whit Verilator (should work with verilator *** FAILED ***)?

I run chisel test and want to generate outputs with verilator. I couldn't find the cause of the error exactly but i think that is related to verilator. This is the part of code that execute the test. It must print some outputs and generate…
Mohamed Abou Messaad
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Rocket chip simulation shows unexpected instruction count

The following two code snippets differ only the value loaded into the x23 register, but the minstret instruction counts (reported by a Verilator simulation of the Rocket chip) differ substantially. Is this a bug, or am I doing something wrong? The…
radiosonde
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Send SystemVerilog $display to stderr

I am using Verilator to incorporate an algorithm written in SystemVerilog into an executable utility that manipulates I/O streams passed via stdin and stdout. Unfortunately, when I use the SystemVerilog $display() function, the output goes to…
Brent Bradburn
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Blocked and non-blocking assignment error in verilator

I'm testing SystemVerilog code using verilator, and it looks like below. output [31:0] data_out1; reg [31:0] data_out1; always @(rst_b or addr1 or data_in1 or write_mask1) begin if((write_mask1 != 32'b0) && (rst_b == 1'b1)) begin …
yongarius
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TIMESCALEMOD verilator error when attempting to add a new black box in chisel

I'm trying to add a new blackboxed verilog module to the chipyard hardware generation framework and simulate it with verilator. My changes pass chipyard's scala compilation phase in which the chisel hardware specification is compiled into verilog.…
benjaminou4412
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Timescale missing on the module as other modules have it Verilator error

I am trying to add an accelerator to the rocket chip framework through the MMIO peripheral. I went through the GCD example and was able to build the basic GCD code. I then replaced the GCD with an accelerator which has it's own Config, Parameters…
CV_Ruddha
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How to trace specific signals using Verilator?

I have a system which I want to trace with Verilator, but using a VCD trace file is highly resource-demanding (hundreds of gigabytes) and time consuming. I changed the trace file type to FST, and the file size is reasonable, but it is still…
ahmad sedigh
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Verilog - bitstream works on hardware but simulation doesn't compile

I am using Verilog to set up FPGA so that it blinks an LED once per second. And this is one way to do it: `default_nettype none module pps(i_clk, o_led); parameter CLOCK_RATE_HZ = 12_000_000; input wire i_clk; output wire o_led; …
71GA
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Verilator - explanation of VerilatedVcdC->dump()

I am reading a wonderful Verilator tutorial and in these slides (page 25) author uses a library call: tfp->dump(tickcount * 10 - 2); I know that tfp is a pointer to a Verilator library object VerilatedVcdC and therefore this call is…
71GA
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