Questions tagged [firrtl]
15 questions
3
votes
1 answer
Chisel/FIRRTL DefnameDifferentPortsException
I recently updated the Chisel version of a big project of mine from 3.1.1 to 3.4.0; however, I am getting a bunch of firrtl.passes.CheckHighFormLike$DefnameDifferentPortsException:
firrtl.passes.CheckHighFormLike$DefnameDifferentPortsException: :…
Mikhail
- 177
- 4
2
votes
1 answer
how to get a critical path / bottleneck analysis of FIRRTL code?
I have some FIRRTL and I want to get a critical path / bottleneck analysis of the code so as to maximize the clock rate by minimizing the critical path.
I can write a weighted topological sort myself, but I do not know the weights that I should use…
Daniel
- 1,861
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2
votes
1 answer
what do "cmem", "infer", and "mport" mean?
I see the following FIRRTL code emitted by Chisel:
cmem mem : SInt<64>[8]
and
infer mport _T = mem[io.address], clock
NOTE: my memory object is named "mem".
However in the firrtl 1.5.2 specification the terms "cmem", "infer", and "mport" do not…
Daniel
- 1,861
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2
votes
1 answer
False "Combinational loop detected"
I'm getting a wrong "CombLoopException" when passing a complex Record (Bundle based on key-value pairs) as UInt and converting the UInt back to the Record by using asUInt() and asTypeOf(...).
When connecting the two Records directly without the UInt…
larluc
- 23
- 3
2
votes
1 answer
How to convert a deprecated low Firrtl Transform to the Dependency API
I am updating a Firrtl transform that looks like this
class RetimeTransform extends Transform {
override def inputForm: CircuitForm = LowForm
override def outputForm: CircuitForm = LowForm
...
to the new Dependency API. Changed the…
Chick Markley
- 4,023
- 16
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1
vote
0 answers
How to move sram to top hierarchy in Chisel3/Firrtl
I make a RISCV core with chisel3. However, when I want to tapeout the core, the SRAMs make a big problem. I should synthesize the logic first, and synthesize the top hierarchy with SRAM as blackbox.
So how can I move all SRAMs to the Top? I have…
DDK
- 136
- 1
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- 11
1
vote
1 answer
what is the idiomatic way to update *part* of a memory element in FIRRTL? this comes up when updating one entry of a line in a cache
Writing a register file in FIRRTL is straightforward: make a memory of machine words and read/write them.
However, when writing a cache, it is different: you typically have a cache line and when writing, only want to update part of the line, a…
Daniel
- 1,861
- 1
- 16
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1
vote
1 answer
Bundle using Mux
I want to use Mux to choose bundle
enter code here
class ComIO extends Bunlde {
val in = Input(UInt(32.W)
val in = Input(UInt(32.W)
}
class EntIO extends Bundle {
val com = new ComIO
}
class Ent extends Module {
val io = IO(new EntIO)
…
HaibaraMegumi
- 11
- 1
1
vote
0 answers
How to emitVerilog from Firrtl with annotations
I am new to Chisel/Firrtl but I find it very interesting!
I am looking for an example of how to take some annotation (like for example one-hot signal) from chisel3 through firrtl onto Verilog where it could be added as a comment.
Mokhtar H.
- 19
- 1
1
vote
1 answer
Chisel: fail to generate verilog while writing a simple combinational logic
I want to implement operation of rotate left shift.
My chisel code :
// src/main/scala/ALU.scala
package cpu
import chisel3._
class ALU extends RawModule {
val io = IO(new Bundle {
val a = Input(UInt(32.W))
val b = Input(UInt(32.W))
…
K.M.T
- 25
- 1
- 5
1
vote
1 answer
Differences between LazyModule and LazyModuleImp
What are the differences between LazyModule and LazyModuleImp?
Like the diplomacy demo under rocket-chip/doc says: The desired hardware for the module must be written inside LazyModuleImp.
But considering following codes:
class A(implicit p:…
Phantom
- 165
- 1
- 8
1
vote
1 answer
Chisel 3.4.2 syncmem and a black box. No memory replacement with --repl-seq-mem option
I run MemtestInst code with --repl-seq-mem option. It has a black box and a SyncReadMem. No memory replacement happens and config file is empty.
If I comment MyBBox line or use older Chisel, replacement works.
Chisel that works:
val defaultVersions…
Anton Sorokin
- 11
- 1
0
votes
0 answers
Exception in thread "main" chisel3.package$ChiselException: Unable to locate the elaborated circuit, did chisel3.stage.phases.Elaborate run correctly
While setting up the Chisel in my linux environment and running a small and_gate test .
I am getting error like this:
[error] Exception in thread "main" chisel3.package$ChiselException: Unable to locate the elaborated circuit, did…
0
votes
1 answer
Initializing IO with a bundle in Chisel 3.5
I am fairly new to Chisel, and is currently attempting to rewrite a Chisel project from Chisel 3.4 to 3.5. The issue I have faced is the project initializes IO()'s with a custom class that extends a bundle like this:
Component with IO:
val io =…
stackmeister
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-1
votes
1 answer
what is the best practice to initialize a FIRRTL memory?
When making a FIRRTL register, it is possible to provide a "with: (reset => ...)" value used to initialize the register.
When making a FIRRTL memory (aka a dynamic register array), there seems to be no corresponding syntax for providing an initial…
Daniel
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