Questions tagged [riscv32]
105 questions
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Why Program Counter in RISC V should be added by 4 instead of adding 0 or 2
Why PC in RISC V architecture connect with PC+4 instead of PC+2 or PC+1. I think it depend on the width of memory cell of the Instruction Memory (IMEM). If the width is 16 bits, then we need to load two adjacent addresses to fill 32 bits instruction…
Khoa Trần
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Calculate nth Fibonacci number using RISC-V (RV32I) compiler without recursion
I have written a code for calculating nth fibonacci number in RISC-V assembly language. It has two parts- fib.s and runtest.s, which loads the value of n into a0 and calls fib, which calculates the nth fibonacci number (without recursion), loads the…
SacredMechanic
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Running GCC compiled code on custom machine. cant find sp initialization in assembly
I was going through .lst while while trying to run gcc compiled code on my custom rv32I machine. I cant find initial vallues of sp
Disassembly of section .text:
00010074 :
register_fini():
10074: 00000793 li a5,0
…
veeYceeY
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Extend risc-v instructions on QEMU
I want to extend the QEMU TCG (tiny code generator) to accept new instructions for the risc-v guest on my x86 machine. However, I have no experience on how the TCG works, so I was wondering if someone can give me some useful pointers on where to…
John
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RISC-V Toolchain Makefile error problem with separators and code. How could I do it correct?
Im having a problem with a Makefile Im trying to create. I just want to create one by one the .elf file then the dump and lastly the bin file and then with a python script convert it to .hex file.
My goal is to actually create the .elf and .hex…
John Liko
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How does risc-v c emulator works?
I'm running a Linux virtual machine based on x86.
and I'm doing cross-compilation(target : RISC-V) with RISC-V compiler and emulator.
I want to know how RISC-V emulator(C file) emulates RISC-V instructions without a real RISC-V cpu.
Sam
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What percentage of instructions in programs run on a RISC architecture are stores, on average?
I am aiming to build a cache for a RISC V core. In deciding the particular design to go with, I wanted to know what percentage of instructions, on average, are store instructions. Knowing this, or even having a very rough estimate, can me help in…
osama zeeshan
- 29
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Are the compressed C.LW and C.SW instructions unable to use labels?
I am writing an emulator of a subset of the RISCV specification, intending to use the compressed ISA as a baseline for my customized 16-bit instruction set. However, riscv32-unknown-elf-as refuses to assemble the C.SW and C.LW instructions with a…
Zee2
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How to detect an overflow on assembler risc-v?
I am trying to implement a recursive factorial function in RISC-V assembly language that raises an error if there is an overflow. However, I am struggling to detect it. Is there a solution for this ?
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Why RISC-V don't have conditional branch equal with immediate value?
Following is most common conditional branch code in my RISC-V assembly project.
li a0, UART1_BASE;
lw t0, UART_INTR_PEND_OFFSET(a0); // Read UART interrupt pending status
andi t0, t0, 1;
li t1, 1; // IMM LOAD
beq t0, t1, LB_process_tx; // UART Tx…
RRON
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RiscV forwarding, why don't we need it?
can someone help me understand why between line 1 and 3 we don't need forwarding (there is no green arrow as between 1 and 2)
I think we need it because sub uses the value of t0 which add determines and both are doing read and write of that value…
user15086117
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1 answer
How can I Convert M-file to RISC-V Assembly code?
I am new to RISC-V. I want to convert that MATLAB code(M-file) to RISC-V Assembly code, can anyone give some suggestions or inputs on how can I do it.
Regards,
Yulia
Yulia
- 31
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RiscV based processor design using HDL
In a project, I have to design a Single/Multi cycle RiscV32 based processor using microprogramming control. But the problem is microprogramming is only applicable for multi cycle processors. Why they have given like "Single/Multi" instead of just…
KS Hewa
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