Questions tagged [riscv32]
105 questions
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How to get the next next element in array in RISC-V?
Instead of incrementing by 4 bytes each time, would I need to increment by 8 bytes? Like for example, addi x9, x9, 8 instead of addi x9, x9, 4 ? Or would we need to consider the size of each word itself?
num_111000
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RISC-V assembly on GCC - Why is a redundant mv command being generated?
I have the following lines
la x14, L2
sw x13, 0(x14)
where the address of L2 is 0x2018.
When I generate the ELF file and inspect it using objdump, this is what I see (relevant parts only):
...
1018: auipc a4,0x1
101c: mv a4,a4
1020: sw …
Plasty Grove
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Why mulh instruction in riscv32 gives 0?
Multiplier = 0xffffffff
Multiplicand = 0xffffffff
Result = 0xFFFFFFFE 00000001 (multiplier * multiplicand)
mulh instruction is expected to give the upper XLEN bits of the result as per RISC-Vs pec. But when I run mulh t0, a0, a1; with multiplier …
RRON
- 1,037
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could tell what i did wrong in the assembly(riscv32), it is printing the warnings wrongly. I'm using the rars simulator
I'm having problems with my code, it just prints "Invalid direction", and the matrix information is correct, my entry was this one .word 3 1 1 1 0 5 2 2 0 1 6 4.
Below is an explanation of how the program should work.
Enemy ships are placed in a…
user10459894
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0 answers
How to model a graph into a riscv custom instruction in c
Instruction recommender tool Graph
I am trying to create a custom instruction and add it to the riscv-gnu-toolchain and spike.
The above link will show the graph that I have generated using rvnewop which is basically an instruction recommender…
Aditya Karthik
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- 5
0
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1 answer
How to clear an exception in handler in risc-v?
Following is my trap routine in FE310 Sifive-Hifive1-Rev B board.
my_trap_routine:
// read mcause
csrr t0, mcause;
// read mepc
csrr t1, mepc;
mret;
Now, I generated a load access fault exception and execution jumped inside the…
RRON
- 1,037
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0
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Why Vacant locations in the address space are never accessible in RISC-V ISA?
I am reading The RISC-V Instruction Set Manual Volume I: Unprivileged ISA and i encountered a very strange statement to me. In subsection 1.4 Memory at the end of fifth paragraph is stated "Vacant locations in the address space are never…
ahmad sedigh
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RISC-V Assembly language. Only printing zero
The following code is supposed to take two lists and put them into one big list (C[10]) and being a beginner in assembly I am unsure as to how to check if my output is correct.
I tried implementing a print to check if the left half works but it only…
ZeinZebib
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- 4
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Using C-program can I access register file of RISC-V?
I want to access the register file of the RISC-V using the C Program.
is there any way I can write and read directly into the register file of the RISC-V using C Program?
afzal junaidi
- 31
- 4
0
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1 answer
Shift 32 bit Numbers on a 16 bit Datapath
How to Shift 32 Bit Numbers on a 16 Bit Datapath
This is a computer architecture question.
My datapath is only 16 bit wide, meaning my ALU can only process 16 bit operands at a time.
My registers are 32 bits wide and are addressable in lower and…
Sun.
- 73
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0
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1 answer
SPI test case in C for Pulpissimo
I am trying to write C test code for SPI peripheral module for Pulpissimo.I have gone through the test case mentioned in pulp-rt examples.
[https://github.com/pulp-platform/pulp-rt-examples/tree/master/periph/spim][1]
But I understand that the…
RISCV
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Assembly what are data, .main and arr?
Today I learnt Assembly language and many instructions like J JAL BNE and so on...
But all of the sudden I saw the following:
data
arr: .word 2, 4, 6, 8
n: .word 9
.text
main: add t0, x0, x0
addi t1, x0, 1
…
user14649084
0
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1 answer
How do i set up instruction & data memory address when using "riscv32-unknown-elf-gcc"?
I designed RISCV32IM processor, and I used "riscv32-unknown-elf-gcc" to generate code for testing.
However, the PC(instruction memory address) value and data memory address of the generated code had arbitrary values. I used this…
doldooly
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0
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1 answer
How is risc-v neg instruction imeplemented?
How is the neg pseudo instruction implemented with only one sub?
I don't understand, as neg is R[rd] = -R[rs1]. But if I have sub, it is R[rs1] - something.
RUI WANG
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0
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Minimum CSR requirements to run Linux
What are the minimum CSR required to run Linux on a RISC-V processor?
The privileged ISA spec does not seem to clarify this point.
OYOunis
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