Questions tagged [riscv32]
105 questions
2
votes
2 answers
What does "not" mean in Assembly-RiscV?
What does not mean in RiscV? I got it after translating some code from C like this:
not a0, t1
user14939321
2
votes
3 answers
riscv-gcc Fails to build [GCC_NO_EXECUTABLES]
I want to use riscv-gcc to implement an Ibex (RISCV core) example on an Arty-A7 but I haven't been able to build it properly.
It's been failing after the 'make' phase. It seems to have something to do with zlib however I'm not so sure since this…
ajabanto
- 23
- 4
1
vote
1 answer
How to run and debug a simple riscv32 bare metal assembly (compiled into elf) using qemu-system-riscv32 and gdb-multiarch? (linker definition issue?)
I'm trying to create a simple assembly program, compile it into an .elf executable, and run+debug it using qemu-system-riscv32 and gdb-multiarch.
There are the two problems that I get, whenever I try running my .elf:
qemu complains that memory…
Gizmo
- 1,990
- 1
- 24
- 50
1
vote
0 answers
RISC-V FENCE Instruction test
The RISC-V Instruction Set Manual in the chapter RV32I Base Integer Instruction Set specifies fence and fence.i instructions. But on official git repository (https://github.com/riscv-software-src/riscv-tests/tree/master/isa) I found only fence.i…
Tarletsky Andrey
- 61
- 4
1
vote
0 answers
GNU RISC-V Embedded GCC throws "x ISA extension `xw' must be set with the versions" error
I can build the c-files from my WCH CH32V003F4P6 microcontroller project with the GNU RISC-V Embedded GCC v8.2.0 toolchain shipped with the Eclipse IDE from WCH (MounRiver Studio). However, if I try to build the same c-files with a similar toolchain…
K.Mulier
- 8,069
- 15
- 79
- 141
1
vote
0 answers
memory initialization with riscv32 ASM
I want to initialize memory block of riscv32 x'10000000 to x'10002000 with 0 to 2048 and variable "key" will take the value from address x'10000400 as the pass word. Because of optimization of assembler, use a pointer can't work, so I try to write…
KabiLink
- 61
- 5
1
vote
0 answers
ri5cy disable interrupts at core level
In ri5cy documentation, it says that :
[§12.1 Interrupts] Interrupts can only be enabled/disabled on a global basis and not individually. It is assumed that there is an
event/interrupt controller outside of the core that performs masking and…
Guillaume D
- 2,202
- 2
- 10
- 37
1
vote
0 answers
Proper gdb backtrace from RISC-V trap / HardFault
I'm using a RISC-V (rv32imac_zicsr) chip and have troubles debugging traps/hardfaults with gdb (riscv-none-elf-gcc toolchain v12.2.0-1 from xPack).
With ARM chips gdb bt lists some, but not all functions leading up to the hardfault.
Assume we have…
Seneral
- 327
- 4
- 12
1
vote
1 answer
__asm__ statement and csrr instruction
I'm trying to write the following code :
#define CONFIG_PMP_SLOTS 16
#define PMPCFG_STRIDE 4
#define CSR_PMPCFG_BASE 0x3a0
void csr_pmp_check(){
for(int i = 0; i < (CONFIG_PMP_SLOTS / PMPCFG_STRIDE); i++)
{
int pmp_cfg;
…
Lovis XII
- 39
- 5
1
vote
2 answers
How to use recursion in Risc-V ? To translate c into Risc-V
We have an assignment to translate the following C code to assembly:
#include
#include
int gcd(int a, int b)
{
int ret;
while (a != b){
if (a > b){
ret = gcd(a - b, b);
return ret;
…
Nicolas Bregantim
- 37
- 5
1
vote
0 answers
is my RISC V interrupt control flow understanding correct？
I'm kinda confused with the syscall code and mcause code. I want to implement a software interrupt on a rv5 cpu with ecall instruction, and the control flow (to my understanding) is :
a7<-system call number
ecall{
mcause<-11
…
Boucii
- 51
- 6
1
vote
0 answers
Perf output is less than the number of actual instruction
I tried to count the number of instructions of add loop application in RISC-V FPGA, using very simple RV32IM core with Linux 5.4.0 buildroot.
add.c:
int main()
{
int a = 0;
for (int i = 0; i < 1024*1024; i++)
a++;
…
lemoncake
- 41
- 6
1
vote
1 answer
how can i disable compress when using riscv32 toolchain
enter image description here
I need only 32-bit instructions but gcc compile my c code with compressing.
I tried -march= options without c but compressed instructions still remain.
How can I get uncompressed(?) instructions?
SweetCaffe
- 21
- 2
1
vote
1 answer
How to debug a factorial function I'm writing in RISC-V assembly?
I'm trying to learn RISC-V and wrote a factorial function, but it's running into a simulator error, hinting at a possible infinite loop. I'm not really sure how to debug my code at the moment, and was wondering if people could drop hints on what I…
norwegian_forest
- 51
- 5
1
vote
0 answers
Unrecognized opcode in creating custom RISC-V instruction
I've downloaded the rocket-chip repo and the corresponding rocket-tools repo. Everything works just fine when I initially build everything.
I've created my own tightly coupled accelerator for the AES algorithm and want to test it using the custom-0…
ttle
- 13
- 2