0

I am aiming to build a cache for a RISC V core. In deciding the particular design to go with, I wanted to know what percentage of instructions, on average, are store instructions. Knowing this, or even having a very rough estimate, can me help in deciding the size of the write buffer when using write-through.

I only need a rough estimate. Estimates on other RISC architectures, like MIPS, may also be useful, I reckon.

osama zeeshan
  • 29
  • 4
  • 2
    Isn't that going to depend entirely on the application at hand? – 500 - Internal Server Error Dec 09 '19 at 11:17
  • Why not look at existing implementations of risc chips? there is no answer here it is heavily dependent on the instruction set which risc-v, mips, arm all have multiple instruction sets, but far more important is the code, it relies heavily on the code and the inputs to the code. How your specific core is designed is also a factor as to how it hits the bus, as well as not just the core but the bus controller(s) and other related factors, prefetchers, etc. (can affect the rate the writes get through). dma engines in the design, etc. – old_timer Dec 09 '19 at 18:21

0 Answers0