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Questions tagged [riscv32]

105 questions
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clang-tidy false positive: stddef.h size_t

On Windows 11 with vscode and the ESP-IDF plugin compiling with riscv32-esp-elf/esp-2022r1-11.2.0/riscv32-esp-elf/bin/riscv32-esp-elf-gcc.exe, if settings.json has "C_Cpp.codeAnalysis.clangTidy.enabled": true, then the standard libraries fail…
Reinderien
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Issue with CSRR instruction in RISCV

I am working on verifying access modes for RISCV CSRs while i am verifying Machine mode Read ony CSRs in assembly code, when i try to access Machine Mode CSR it needs to raise exception but in my case i placed two back to back CSRR insruction where…
Krishna
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Building the Linux kernel to set up riscv32

I was trying to build the kernel from the linux repo v5.12 to set up an image for the qemu emulator and I keep getting this error ./arch/riscv/include/asm/irqflags.h: Assembler messages: ./arch/riscv/include/asm/irqflags.h:28: Error: unrecognized…
kidusworkneh
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OpenMP Runtimes

Can anyone recommend a compiler and runtime that will support OpenMP and OpenMP offload on RISC-V processors? I am not interested in running Linux on the RISC-V processors due to overhead and am seeking a much lighter weight runtime implementation…
JimW
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Why isn't my code outputting text in assembly code?

.data word: .word 2,3,4,5,6,7,8,9 ace: .asciiz "ace" queen: .asciiz "queen" king: .asciiz "king" jack: .asciiz "jack" clubs: .asciiz "clubs" diamonds: .asciiz "diamonds" hearts: .asciiz "hearts" spades: .asciiz "spades" rank_format: .asciiz…
Lou REEDME.md
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RISC-V two lables on the same line?

Does anyone know if its possible in any way to put two labels on the same line when writing in RISC-V. I can't seem to find an answer on the documentation. Here is an example Where I want to compute the sum of every integer in the array. v: .word…
Fausto Zamparelli
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How do you read text (.txt) files in RISC V (using RARS simulator)?

I have a text file called dna.txt which contains ACGGTGCTGTATCCATATCCGTTAACTCTCTTGTGTCACC. I want to count the occurrences of characters C and G in the text file, and the length of the original string. I want the program to read the input from a…
lowrain
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Why does Vivado not recognise packages without modules in System Verilog?

I have a lengthy enum of opcodes that I want to include in a package so that it can be used in multiple locations throughout the project, this is: typedef enum logic [6:2] { LOAD = 5'b00_000, LOAD_FP = 5'b00_001, CUSTOM_0 = 5'b00_010, …
Lyndon Alcock
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The 32-bit program cannot be executed with RISC-V Spike. Can't Execute 32-Bit Program on RV64 Hot

The following software has been built, installed, and passes. RISCV-GNU-TOOLS (both 64, 32bit), Spike, Riscv-PK (32bit). If you try to execute the C language program with RISCV32 and execute it in Spike, you will get an error as follows. What should…
Satoshi921
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What is the simplest way to programming, debugging and executing risc-v assembly code using Qemu?

I don't access to any RISC-V hardware, so, what is the simplest way to programming, debugging and executing risc-v assembly code using Qemu? As I am reading the RISC-V edition of the Computer Organization and Design book, I prefer the 32 bit…
user153245
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KONG [API gateway] support on RISCV64

Does RISCV64 support KONG [API gateway] ? Does RISCV64 support luaJIT and openresty [dependencies of KONG] ? I am using EdgeX with security on RISCV architecture and for that I need to use KONG as an API gateway. please let me know if riscv64…
dipshi singh
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Timer Interrupts (CLNT) and __stack_chk_fail with RISC-V

I'm writing an emulator and I'm having a bear of a time figuring out exactly what the CPU should do. I have a system that works, almost all the time. I can run the NOMMU RV32 Linux kernel if I very carefully pick my CLNT:CPU timer ratio to get…
Charles Lohr
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How to install riscv32-unknown-elf-gcc on Debian-based Linuxes

I'm using a rv32ima bare metal processor, and I need to use riscv32 for it. I've been struggling to find the right combination of packages to compile for it. The closest I've found was: apt-get install gcc-multilib gcc-riscv64-unknown-elf And…
Charles Lohr
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RISC-V: How to fix "file format not recognized" when disassembling a .img file?

I'm playing with RISC-V. I have a .img file and I want to disassemble it into a .asm file, so I ran the following command: > riscv64-unknown-elf-objdump -d xxx.img > xxx.asm However, I got this issue: riscv64-unknown-elf-objdump: xxx.img: file…
Hengzhuang Li
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How to prevent rust entry point _start to not push return address into stack before stack is set?

Following is the _start entry point for my embedded rust code. The _stack_start comes from linker script. #[no_mangle] pub fn _start() -> ! { extern "C" { static _stack_start: u32; } unsafe{ let sp1 = &_stack_start; …
RRON
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