Questions tagged [riscv32]
105 questions
1
vote
1 answer
Executing dynamically generated code on RISC-V
I am writing a Forth-like language for RISC-V and naturally that means I need to have a way to allow the users to define new words and execute them.
But I am struggling to find a way that will allow users to execute dynamically generated code…
adrianmcmenamin
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1
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1 answer
Compiling rv32i Code includes compressed Instructions
Im trying to compile bland c code to an elf format executable by a RV32i processor.
However when I enable optimizations (-Os or -O2) the resulting assembly contains compressed Instructions which I can not execute.
All my selfmade code is being…
Sun.
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- 7
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1 answer
How do I store or load by byte unit into memory when using “riscv32-unknown-elf-gcc”?
I want to operate memory load or store in BYTE (8-bit) or HALF WORD (16-bit) unit.
So I made the C code as below and compiled it using "riscv32-unknown-elf-gcc".
void fun3 (void) {
char i,j;
i = (char)*(volatile unsigned int *) 0xf10007f8;
…
doldooly
- 55
- 5
1
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1 answer
Access rights in RISC-V linkerscripts
When programming ARM-based microcontrollers, I'm used to see a MEMORY{..} segment in the linkerscript like this:
MEMORY
{
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 128K
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 32K
}
The access rights are…
K.Mulier
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1 answer
How is the 34 bit physical address space accessed in a RISC-V 32 bit system when virtual memory is disabled?
In the RISC-V 32 bit ISA, the physical address space is 34 bit with a 32 bit virtual address space. When virtual memory is enabled in supervisor mode the 32 bit virtual address is translated by accessing the page table, yielding a 34 bit physical…
Joshua McKelvey
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- 4
1
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2 answers
RISCV32 vs RISCV64
What are the differences between Riscv32 & Riscv64? I have been looking into the ISA docs, but cannot find it mentioned clearly anywhere, so pretty confused now.
I cannot find any docs about this from google, unfortunately. Any pointer?
aqua2019
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- 7
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1 answer
RISC-V: Do 12-bit immediate logical operations operate on the whole register?
I am trying to write a simulator for a RISC-V CPU and can not find a definitve answer to my question.
Let's say I want to use
ANDI rs1, rd, 0xFFF
with rs1 containing 0xFFFFFFFF and the immediate value being 0xFFF.
Does the ANDI operate on the…
Klickmann
- 130
- 8
1
vote
0 answers
How do I reverse a 32 bit register in riscV (32 bit), is there a command for it?
I am using the venus simulator for writing code. I can't find a specific instruction for rotation or reversing a register.
fortune7
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- 2
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RISC-V: operation with a0 changes other register values
I'm currently doing a small project on risc-v.
The problem is that, in a function, when I do something like this,
foo:
...
lw a3, 4(sp)
srli a2, a2, 16
srli a4, a4, 16
add a0, a2, a4
ret
after executing add a0, a2, a4…
TAYTAY1313
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1
vote
1 answer
QEMU riscv32 virt machine, how to access the screen?
I want to use QEMU to setup a bare metal riscv32 machine and so assume I need to use the '-machine virt' option. How do I setup so I can output to a screen? Either a console style output where I provide strings to be output, or a VGA device where I…
Phil Wright
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C code with vector instrinsics for Riscv Vector
I have simulated bare-metal General purpose Riscv programs on spike. Now I want to run bare-metal vector program on spike but I think that the C program that will be used to cross compile and generate a log file through spike will be built…
0
votes
1 answer
What determines how a 64-bit function argument is split between registers on RISC-V 32?
I'm currently trying to learn risc-v by use of the book "RISC-V Assembly Language Programming Using the ESP32-C3 and QEMU" by Warren Gay. In the book it states that when a 64-Bit value is passed on a 32-Bit platform the low-order 32 bits are loaded…
ass-embler
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make error at Building C object common/CMakeFiles/common.dir/demo_system.c.o
I'm trying to builds the software that I can later use as memory content for the Ibex
running in the demo system.
After the following commands:
mkdir -p sw/build
pushd sw/build
cmake ..
make
"make" gives me the:
[ 3%] Building C object…
shekhar compeng
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- 1
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0 answers
Attempting to build riscv64-unknown-linux-gnu crashes my session. How can I debug this?
I'm trying to run a RISCV Linux system in QEMU, following the official steps for it, here: https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-qemu.html
My problem starts where most people's problem starts, in the
cd linux
git…
Francisco Ayrolo
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- 5
0
votes
1 answer
Reading an RGB formatted file into a buffer in RISCV (32-bit) assembly
I'm trying to read the RGB values from the file into an array, but when I check the buffer it's full of zeros instead of the values. First I tried it in C and then, implemented it in riscv assembly. I'm not sure what's causing this.
Here are the…
emirbalci
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