Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs
Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs
Questions tagged [questasim]
90 questions
1
vote
1 answer
binary write SystemVerilog
I tried write binary file in SystemVerilog in my testbench.
int file = $fopen(path,"w");
if (!file) begin
$error("File could not be open: ", path);
return;
end
$fwrite(file, "%u", 32'h4D424D42);
$fclose(file);
And get result:
02 0c 02…
Андрей Кущенко
- 21
- 2
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1
vote
1 answer
call questa sim commands from SystemVerilog test bench
I want to call questa sim commands like add wave ,add list, write list from my SystemVerilog test bench
task add_files_to_list();
add wave -position insertpoint sim:/top/clk
add list sim:/top/clk
write list -window…
user3627129
- 11
- 3
1
vote
1 answer
Unexpected Nonexistent Associative Array Warning in Questa after rollover
Normally in Associative Array, Rollover issue is taken care by the tool. But in QuestaSIM, I am facing the issue, like if key of the Associative Array is 64 bit variable, then after overflow, it does not store data properly.
Suppose index is…
Karan Shah
- 1,912
- 1
- 29
- 42
1
vote
1 answer
Simulating .xci Files in Questasim
I'm on Linux, I'm using questasim 2012.2b. I wrote in VHDL the following:
dsp: entity work.dsp_c -- a*b+c, 12bit
port map
(
clk => clk_i,
a => a_dsp,
b => b_dsp,
c => c_dsp,
p …
fiz
- 906
- 3
- 14
- 38
1
vote
1 answer
Systemverilog: Simulation error when passing structs as module input\outputs
I am trying to pass one structure as an input and get the output in another structure. However I am having some issues during simulation. The following example code compiles fine in questasim, however the simulation gives the following…
user3716072
- 187
- 1
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- 14
1
vote
2 answers
Syntax for looping through lower dimension of multidimensional associative array in a constraint
class ns_data_struct;
rand bit [63:0] ns_size = 64'h0000_0000_0000_0800;
endclass : ns_data_struct
class conf;
ns_data_struct ns_data[];
function new();
ns_data = new[5];
foreach (ns_data[i])
ns_data[i] = new();
…
Karan Shah
- 1,912
- 1
- 29
- 42
1
vote
2 answers
Installing UVM 1.2 in Questasim 10.2 windows
I have downloaded the UVM 1.2 from Accellera website. I am using Questasim 10.2 and my UVM version is 1.1d.
Now I copied the UVM 1.2 folder into C:\questasim_10.2c. Then I changed the
mtiUvm = $MODEL_TECH/../uvm-1.1d
line in modelsim.ini to
mtiUvm…
Vineeth
- 111
- 2
- 11
0
votes
1 answer
What should I do to make the interface visible to some components?
Recently, I am trying to copy a UVM architecture that is used to verify a router of NoC (network on chip). Since I want to verify my router of NoC, the architecture doesn't change much. However, it doesn't work. The following information comes from…
benjstark
- 83
- 4
0
votes
1 answer
Module's parameter initialization troubles (updated)
I want to have universal function to initialize same module with different parameters. One of them is packed array with size depends on another parameter.
I've tried something like this:
package my_pkg;
class helper #(
parameter p_WIDTH…
Don Rumata
- 11
- 2
0
votes
0 answers
Does modelsim support non- ascii project paths?
The modelsim documentation doesn't mention about the allowed project paths. Does anyone know if the non-ascii projects are compatible with modelsim?
I was getting an error on modelsim when I try to cd to non-ascii path
navyas
- 9
- 1
0
votes
2 answers
Formatting $info
How can I format the output of $info, $warning, etc. of Verilog code?
By default (at least Questa) shows messages on two lines, and I need to get rid of line changes, file paths, and other stuff that is basically just causing noise in my…
jarno
- 137
- 1
- 10
0
votes
1 answer
No data message in ModelSim
module barrel(W,Y,S);
input [3:0] W;
input [1:0] S;
output [3:0]Y;
wire [3:0]T;
assign {T,Y}={W,W}>>S;
endmodule
module sim();
reg [3:0] W;
reg [1:0] S;
wire [3:0] Y ;
barrel sim1(W, S, Y);
initial begin
…
grandslam47
- 9
- 2
0
votes
1 answer
Dynamic generation of signal spies in testbench
I have a .txt file that contains certain signals that I want to monitor in my testbench during the application of some stimulus.
I am creating an initial block in which I am reading the file and then I try to generate a init_signal_spy() for every…
ex1led
- 427
- 5
- 21
0
votes
0 answers
Is it possible to testbench VHDL designs with verilog
I am trying to testbench a VHDL Design in Verilog. I am using Questa but I am unsure how to import the signals from the VHDL Design into the Verilog testbench if that is possible. Here is my code so far. I also should mention I am aware of…
Nmarks
- 11
0
votes
1 answer
Redirecting output of tcl proc to file and output (like tee) Part 2
I am using tee from https://wiki.tcl-lang.org/page/Tee to redirect file output from my procedures. I need to redirect both stdout and stderr to the file.
Using the input from Redirecting output of tcl proc to file and output (like tee) I arrived…
Jim Lewis
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