Simulating .xci Files in Questasim

Question

I'm on Linux, I'm using questasim 2012.2b. I wrote in VHDL the following:

dsp: entity work.dsp_c -- a*b+c, 12bit
port map 
(
    clk         => clk_i,
    a           => a_dsp,   
    b           => b_dsp,
    c           => c_dsp,
    p           => p_dsp  -- full precision 
);

Everytime I try to simulate the above with questasim, it throws up an error when compiling saying:

# Error in macro ./mkProject.tcl line 11
# /software/CAD/Mentor/2013_2014/Questa/HDS_2012.2b/questasim/linux_x86_64/vcom failed.
#     while executing
# "vcom hdl/calc.vhd"
#  quit

# ** Error: Library xbip_dsp48_macro_v3_0 not found.
# ** Error: Unknown identifier "xbip_dsp48_macro_v3_0".
# ** Error: VHDL Compiler exiting

It refers to the code above on the line it fails on.

When rummaging around, I did find a file called : dsp_c.vhd which looks like a simulation wrapper for the .xci file.

I then try to locate the library, I found a folder called xbip_dsp48_macro_v3_0 with two files inside: xbip_dsp48_macro_v3_0.vhd xbip_dsp48_macro_v3_0_vh_rfs.vhd

So I include those in the project too, it gives me the error:

xbip_dsp48_macro_v3_0.vhd(46)): in protected region

Any idea what could be going wrong or what I might need to include? Is my questasim perhaps too old?

MORE INFO

Tried getting the compiled files this way via tcl:

compile_simlib -simulator questa

Produces a folder of all the IPs with their corresponding compiled blocks. Now I though initially I could just add to the .dep:

src ../cgn/dsp_c/dsp_c.vhd

I get this when running make project:

dsp_c/dsp_c.vhd(56): Library xbip_dsp48_macro_v3_0 not found.

So I tried including the libraries:

src ../cgn/dsp_c/xbip_dsp48_macro_v3_0/hdl/xbip_dsp48_macro_v3_0_vh_rfs.vhd
src ../cgn/dsp_c/xbip_dsp48_macro_v3_0/hdl/xbip_dsp48_macro_v3_0.vhd

Says it’s protected:

dsp_c/xbip_dsp48_macro_v3_0/hdl/xbip_dsp48_macro_v3_0.vhd(46)): in protected region.

More More Info

I got vivado to generate the library, located in the folder dsp_c:

dsp_c.dcp   dsp_c_funcsim.vhdl  dsp_c_stub.v     dsp_c.xci  synth   xbip_dsp48_wrapper_v3_0  xbip_utils_v3_0
dsp_c_funcsim.v  dsp_c_ooc.xdc      dsp_c_stub.vhdl  dsp_c.xml  xbip_dsp48_macro_v3_0   xbip_pipe_v3_0

My tcl script looks like this:

source firmware/cfg/lib_mappings.tcl

vlib work
vcom firmware/hdl/mydsp_c.vhd

Results

Modified to this:

vlib work
vlib dsp_c/xbip_dsp48_macro_v3_0
vmap dsp_c/xbip_dsp48_macro_v3_0

Then ran it ...

# do mkProject.tcl 
# Modifying modelsim.ini
# ** Warning: (vlib-34) Library already exists at "work".
# ** Warning: (vlib-34) Library already exists at "dsp_c/xbip_dsp48_macro_v3_0".
# Reading modelsim.ini
# "dsp_c/xbip_dsp48_macro_v3_0" maps to directory ./dsp_c/xbip_dsp48_macro_v3_0. (Default mapping)

..........

# -- Loading package NUMERIC_STD
# ** Error: firmware/cgn/dsp_c/dsp_c.vhd(56): Library xbip_dsp48_macro_v3_0 not found.
# ** Error: firmware/cgn/dsp_c/dsp_c.vhd(57): (vcom-1136) Unknown identifier "xbip_dsp48_macro_v3_0".
# ** Error: firmware/cgn/dsp_c/dsp_c.vhd(59): VHDL Compiler exiting
# ** Error: vcom failed.

Answer 1

An xci file is a Xilinx specific IP description file and will not be recognized by any simulator. To be able to perform behavioral simulation of the IP described by the xci file a simulation model has to be generated first. The simulation model will consist of a number of VHDL files which have to be compiled into specific libraries.

With ISE/Coregen it used to be that there was only one VHDL file generated for an IP and the IP had only dependencies on the pre-compiled XilinxCoreLib library. With Vivado however there is no longer a XilinxCoreLib library and every time a simulation model of a specific IP is generated every dependency is also generated into the same folder.

It is possible to generate simulation model and an associated a list of files and libraries to compile using Vivado TCL scripting: https://github.com/LarsAsplund/vunit/blob/master/examples/vhdl/vivado/tcl/extract_compile_order.tcl

The above TCL script is part of an example shipped with the VUnit VHDL testing tool that demonstrates how to automatically generate models of and simulate Vivado IPs. The project and output_file variables are set from the command line to the script as the complete example calls the script via Python but can be replaced by hard coded values. The output is a text file with LIBRARY, FILE_NAME of all files in the order they need to be compiled. In my previous projects I have used this method to generate and compile behavioral models of an entire Vivado project.