Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs
Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs
Questions tagged [questasim]
90 questions
0
votes
1 answer
VHDL unconstrained records in system verilog testbenches
The design to be tested is written in VHDL and uses unconstrained records like this for its ports:
type forward_stream is record
data : std_ulogic_vector;
-- further members
...
end record;
These ports should now be driven from a…
ted
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1 answer
Modelsim export wave (bitmap) batch mode
Currently I run Mentorgraphics Modelsim in batch mode for a few nightly simulations.
My simulations run fantastic and in my transcript files I can see all errors/warnings/etc. but it would be nice to see the waveform for every simulation in a image,…
michi.b
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1 answer
How can I compile Xilinx Vivado's simulation libraries for e.g. QuestaSim?
I want to compile the Xilinx Vivado simulation primitives for QuestaSim (ModelSim). The documentation lists a TCL command, but I would like to use a common shell command like the old one for ISE:
\bin\nt64\compxlib.exe -family all -…
Paebbels
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1 answer
How to do linting with Questasim?
I was using linting tool HAL from Cadence. Now I have to use Questasim. But I don't know about the tools or switch that I can use for linting.
Is there any tool from Mentor(Questaism) like HAL from Cadence (HAL is a separate tool for linting…
AnuragChauhan
- 143
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- 15
0
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3 answers
Overriding the built-in sample method in systemverilog
My question is whether concurrently sampling a coverpoint by multiple threads (after having overridden the buit-in sample method) creates any side-effects.
In more detail, consider the following code:
covergroup p_cg with function sample(bit [1:0]…
Stast
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- 1
0
votes
1 answer
vsim command in Questasim for test pass/fail information
Is the pass/fail test information for the Questa simulation recorded in the .ucdb file? If so is there a vsim command that extracts that information?
user3293692
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0
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2 answers
Dynamic Coverpoints in Coverage Systemverilog
class conf;
typedef struct packed
{
int ns_size;
int limit;
} ns;
int num_ns_supported;
ns num_ns[];
function new(input int s=5);
num_ns_supported = s;
num_ns = new[s];
foreach(num_ns[i])
begin
…
Karan Shah
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0
votes
1 answer
How to get source of a sampled bin in Coverage in QuestaSIM
I'm using QuestaSIM and have a merged coverage report from regression.
From my merged coverage report, how can I trace a sampled bin back to its simulation (test name & seed value)?
Karan Shah
- 1,912
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- 29
- 42
-1
votes
1 answer
Exclude some design unit from code coverage on Questasim
I run a code coverage on questasim and I got ucdb file as output. But I need to exclude code coverages of some modules that connect to the top module.I don't need some of modules to be covered which this I can improve coverage report.
How can I do…
Buğra Tufan
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-1
votes
1 answer
Questasim - Is it possible to log and reload signals on new design?
I am running a test (UVM) with lot of components. It is a Top-Level test, however I am debugging an internal module and I am only interested in the signals of the interfaces connected to that module. Since it is a TL it takes long time since I get…
Hellzzar
- 185
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-1
votes
1 answer
How to display list of Verilog force from Modelsim / Synopsys simulator?
For the ncsim https://community.cadence.com/cadence_technology_forums/f/functional-verification/17382/ncsim-how-to-display-list-of-verilog-force-from-inside-verilog-testbench.
How to track the list of Verilog force, is there any simulator/language…
Mana
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- 2
- 8
-1
votes
2 answers
Optional Randomization of enum variable
I am writing a Testbench using Systemverilog and I want to have the freedom to choose in each test to either randomize some variables or specify their value (from a .do file or from command line). Is there any option in Systemverilog to do this?
user281270
- 15
- 7
-1
votes
1 answer
TCL wildcard/glob usage within file name
I have code that is like this:
...
proc myProc {first last} {
for { set i $first } { $i <= $last } { incr i } {
set i_cur "PlainText$i"
[glob ./../myDir/${i_cur}*]
}
}
When I run this, any file that has nothing…
Raj
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-2
votes
1 answer
How do I invoke Clock-Domain Crossing in Questa CDC?
Is there a command to invoke Clock Domain Crossing (CDC) in Questa CDC?
I am looking for something like in midelsim .vsim for simulation, in cadence simvision.
