0

I am trying to testbench a VHDL Design in Verilog. I am using Questa but I am unsure how to import the signals from the VHDL Design into the Verilog testbench if that is possible. Here is my code so far. I also should mention I am aware of signal_spy() but I am unable to use this because this relies on the path of specific variables which might change in my project.

Verilog testbench:

`include "tb_zb01.vh"
`timescale 1 ns / 1 ns

module tb_zb01;

   //***************************************************************************
   // test bench signals
   //*************************************************************************** 
   reg               clk100;
   reg               rst_sync_100;
   
   //***************************************************************************
   // clock generation, 100 MHz
   //***************************************************************************
   initial begin
      clk100=0;
      forever begin
          #5; clk100 = ~clk100;
      end
   end
   //***************************************************************************
   // generate a reset in the all domains
   //***************************************************************************
   initial begin
      rst_sync_100<=0;
      repeat (10) @(posedge clk100);
      @(posedge clk100) rst_sync_100 <= 1;
      repeat (21) @(posedge clk100);
      @(posedge clk100) rst_sync_100 <= 0;
   end
   //***************************************************************************
   // this is the DUT
   //***************************************************************************
   zb01_top dut(
         // misc
         .i_clk100                   ( clk100 ),
        .i_rst_sync_100             (rst_sync_100)
         );
   
endmodule // tb_zb01

VHDL Design:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 

library work;
use work.epack.all;


entity zb01_top is

generic(
      SUPER_SECRET_RUN_FAST : integer := 1
      );


port(
    -- Outputs
    o_led_drv_01     : out std_logic;
    -- Inputs
    i_clk100       : in  std_logic;
    i_rst_sync_100 : in  std_logic
    );

end entity;
 
architecture rtl of zb01_top is

signal counter: natural range 0 to 100000000 := 0;
signal alive         : std_logic := ZERO;

begin


process(i_clk100)
begin


if (i_clk100'event and i_clk100 = ONE) then
      if (i_rst_sync_100 = ONE) then
        counter    <= 0;
        alive      <= ZERO;
      else
        if (counter = (HALF_CYCLE - 1)) then
          alive   <= not alive;
          counter <= 0;
        else
          counter <= counter + 1;
        end if;
      end if;
    end if;
end process;

o_led_drv_01      <= alive;


end architecture;
Greg
  • 18,111
  • 5
  • 46
  • 68
Nmarks
  • 11
  • There is no standard way to link Verilog and VHDL. Several simulators have implanted their own ways to link them, so you will need to read vendor specific documentation. – Greg Jul 08 '22 at 16:11
  • 1
    What do you mean by "import the signals from the VHDL Design into the Verilog testbench"? Do you mean hierarchical reference? It would be kind of a weird, undefined thing to try to hierarchically reference something that crosses a verilog/VHDL boundary... – Ryan Johnson Jul 08 '22 at 17:02

0 Answers0