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Questions tagged [questasim]

Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs

Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs

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How to override localparam? -GPARAM=VAL not working

I know we can override a generic/parameter in Verilog/SystemVerilog using vsim's option -GMYPARAM=VALUE. This doesn't work for a localparam and the use of localparam in the module to prevent the change of the value isn't allowed. mymod #( …
Alexis
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difference between "Coverage summary by istance" and "Design Unit Coverage Details"

In an FPGA project what is the difference between: Coverage summary by istance Local Istance Coverage Details Recursive Hierarchical Coverage Details Design Unit Coverage Details
KemKing
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Simulation Waveform in Intel Questas_fse/Quartus II doesn't update outputs

I'm attempting to run Quartus II ( Quartus Prime Version 21.1.0 Build 842 10/21/2021 Sj Lite Edition) on linux Pop OS 21.10. I fail to produce result on output from Questas simulation run from the Simulation Waveform Editor. Project Settings I have…
NRagot
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modelsim/questa ERROR: UI-Msg: (vish-4014) No objects found matching '/*'

Any ideas on how to get modelsim/questa to include all "Objects" so that they will be in the WLF? I tried -novopt and +acc without any success?? my questasim/modelsim "do script" is exiting early because I tried to log all signals into a wlf file…
pico
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Element not found for associative array index in constraint

I'm trying to randomize the contents of an associative array, and I ran into an error: element not found for associative array index in constraint How do I initialize these indices and then randomize their values? module top; class TFoo; typedef…
lonely
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My testbench only shows don't cares for my inputs

When I test my dataflow module, all my inputs come out as don't cares. I'm not sure where the problem lies. Could it be my equations or my testbench itself? Here is my code. Dataflow: module…
manny123456
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SystemVerilog hierarchical reference in nonblocking assigment

I'm seeing strange behavior in my testbench where a nonblocking assignment is acting as a continuous assignment instead of outputting the RHS delayed by one cycle. My testbench binds a module "cov" to the DUT at cpu.cache via bind cache cov cov_top,…
Melandru's Square
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SystemVerilog: Collapsing and & on an array of interface ... Collapsing or | on an array of interface

I am trying to change some of my code pretty drastically. Everywhere where I am using a widely used struct in a module port signature, I would like to replace with a interface (if appropriate). One logical operation that I have not figured out is a…
ik631
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Evaluation of SystemVerilog assign statements in RTL simulation

I'm trying to understand why the statement coverage of two SystemVerilog assign statements could differ from each other when the condition expression is the same for both of the statements. Consider the following: As shown, the condition expression…
yildizabdullah
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assign statement in Questa Sim yields x as output

I wrote a module that should "or" a signal with a delayed version of itself. But, when I simulate my design, the output always goes x instead of 1. I have no idea why. Here is how I wrote my design: module DUT( input data_in, input dw, input…
Fabian
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Running a test in Questa from Makefile

I have written a Makefile to run tests in questasim. I am using the following commands. vsim -l transcript -voptargs=+acc test -do $(WAVEDIR)/$(WAVE_FILE) This helps to open the questa window and simulate the test case. With thin the questa…
Saikat Chatterjee
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I am writing a SystemVerilog Testbench for a module that models a schematic, but don't know why transcript window saying no connection to port Y?

The Following schematic is what I have modeled my module from. This is a SystemVerilog HW assignment in which we must use contiuous assignment(s). The signature model was given to us. Note there is no delays in the circuit. The problem I am having…
CEStudent
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Running a regression with shell script and make utility

I want to run a regression with a shell script which should start each test via make command. The following is a simple version of my script: #!/bin/sh …
yildizabdullah
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How to check values of signals at all component hierarchy levels in VHDL

Typically I do this with TCL and simulator commands to make sure all signals are initialized to a valid value during reset, but I want to know if there's a way to accomplish this in pure VHDL. Here's a TCL-based example. It is very convenient to use…
user_007
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Create questasim/modelsim project from the command line

I'm trying to write a makefile for compiling and simulating some vhdl code. Is there a way to create a project from linux/windows command line ? It is straightforward if you open the tool and run "project new" but there's no documentation for…
Jim
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