Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs
Mentor Graphics software to perform a functional simulation of a VHDL or Verilog HDL designs
Questions tagged [questasim]
90 questions
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1 answer
Passing $args as a substitution for vsim arguments gives an error
I want to use $args as a substitution for some of the vsim arguments.
** UI-Msg: (vish-3296) Unknown option '-assertdebug -classdebug'
vlog -sv time_diff_test.sv
vopt time_diff_test +acc -o dbgver
set args "-assertdebug -classdebug"
vsim dbgver…
eminakgn
- 35
- 3
1
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1 answer
Setting signals length using received parameters in SystemC
context
I'm making a simulation environment with systemC co-simulated with verilog/VHDL RTL modules using modelsim/questasim
My Verilog modules use parameters to set up each module
My VHDL modules use generics to set up each module
My systemC…
NicolasDg
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1
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1 answer
System Verilog: clocking block effects propagation
Consider the following SV code snippet:
module clocks();
logic a ;
bit clk =0;
initial begin
forever #1ns clk = ~clk ;
end
clocking cb@(posedge clk);
default input #1step output negedge;
output a;
endclocking
…
atadocca
- 21
- 4
1
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1 answer
EDA Playground EPWave $dumpfile error: no vcd file found
I am trying to simulate my design in EDA Playground. I tested my design file and testbench file in my local computer using ModelSim (not from EDA), and it was successful. However, I tried to do the same with EDA Playground. It is successfully…
efe373
- 151
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1
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1 answer
Modelsim/Questasim unit delay simulation
I would like to launch an unit delay RTL simulation using Questasim 10.1. I've looked how to compile the design and I see there is an option +delay_mode_unit for compiling verilog files. My design is vhdl.
Is there an option for this kind of design?
Mxm89
- 21
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1
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0 answers
Modelsim ( Questasim 10.1) save results from a certain time and see schematic data
I ve launched a simulation for reproducing a bug. The bug happens after 1s of simulation time and so the simulation last too much.
Is there a way to save only the waveform and the other infos from a certain point of the simulation (i.e. after 1s)?…
Mxm89
- 21
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1
vote
1 answer
8 bit carry lookahead adder error with SystemVerilog in Questasim using two 4 CLA's
I keep getting an error when I simulate the CLA4Top, CLA8Top and the test.
The testbench was given and the entire project compiles. For the CLA4Top I thought it looked like "cout" is coming out to be correct but "sum" is not matching the expected…
MignolaFan
- 31
- 4
1
vote
2 answers
In Modelsim/Questasim is there a way to increase the thickness of the wave lines?
Using Modelsim/Questasim 10.6b with a 4K monitor makes it difficult to see the lines for signals, especially std_logic signals, vectors are a little better.
I was able to increase text size via edit->preferences but haven't found anything similar…
Joe
- 21
- 3
1
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2 answers
Realtime CPU clock vs High Frequency Software clock
I am curious to learn about the technology which is used in generating software clock in simulators. The frequency of my machine is only ~2.4GHz but I can generate up to 500THz clock using a simulator(Refer below system Verilog snippet ).
`timescale…
Sreejin TJ
- 177
- 12
1
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2 answers
How to generate a detail report of functional coverage in Questasim?
How to generate the detailed coverage report of functional coverage? I am using following command to simulate my code :
vlog -64 -work work -vopt +notimingchecks +cover +fcover -f pcie_jammer.f
vsim -novopt -c
-t ps…
Himanshu Khandelwal
- 21
- 1
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- 6
1
vote
1 answer
VHDL 2008 can't drive a signal with an alias of an external name
Please take a look at the following code, specifically the 3 commented lines at the end. I simulated this with Questasim 10.6c:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alias_extname_driving_signal is
port(
clk…
Michael Grover
- 87
- 1
- 9
1
vote
1 answer
Unable to access dimensions of svOpenArrayHandle
I have a multidimensional dynamic unpacked array in my SystemVerilog testbench and am passing this into C code as an argument using DPI-C. I am using Questasim 10.4b. Following the flow of Questa, I ran -dpiheader to generate the header file and…
noobuntu
- 903
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- 42
1
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1 answer
Binding a checker in SystemVerilog
I would like to bind a checker construct to a VHDL module (in QuestaSim) to ensure some verification properties, without having to declare and bind a more (complex) module/interface/agent structure.
Without further ado I present you the example code…
anthrazithe
- 76
- 7
1
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2 answers
Why does this FSM not reach 100% code coverage?
I have the following simple FSM description in VHDL:
library ieee;
use ieee.std_logic_1164.all;
entity coverage1 is
port (
clk : in std_logic;
rst : in std_logic;
req : in std_logic;
ack : out std_logic
);
end entity…
Paebbels
- 15,573
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1
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1 answer
How do I know which Systemverilog macros are defined when using Modelsim or Questasim?
I'm using Questasim 10.4c to simulate a Systemverilog design that uses the `ifdef compiler directive at a bunch of places. Example:
`ifdef FOR_SIMULATION_ONLY
`endif
After compiling, I haven't found any way to get Questasim to be able to…
Michael Grover
- 87
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