Highest Voted 'questasim' Questions

0

votes

1 answer

How to load coverage_db?

I'm trying to write a functional coverage for my design. I wrote needed covergroups, but now I faced with difficulties to transport my coverage between test runs. Here a few code examples: `include "uvm_macros.svh" package t; import…

asked Oct 30 '19 at 09:04

Андрей Солодовников

277
3
15

0

votes

3 answers

Array of parameters in systemverilog

I try to instantiate array of parameters, e.g. module top(); parameter array_size = 10; parameter par_array [array_size] = '{array_size{12}}; initial begin $display("%d",par_array[array_size-1]); end endmodule But when I…

system-verilog questasim

asked Sep 26 '19 at 14:23

Андрей Солодовников

277
3
15

0

votes

2 answers

Cadence IUS simulator options

What is the difference between -INcdir and +incdir+ options in NC simulator? Below is the example command from the Makefile. As far as I know the testbench directories are included using -INcdir and the source code file directories are included…

system-verilog modelsim cadence questasim synopsys-vcs

asked Aug 05 '19 at 16:53

Sreejin TJ

177
12

0

votes

1 answer

How to specify height of waveform in Modelsim/Questasim?

I'm using QuestaSim 70.7b; And I can not change the height of waveform signal.. I've tried many options, like this: add wave -radix hex -format analog-step -scale 100 -height 100 -color gold /bin_top_tb/clk But nothing happen, just height of the…

verilog system-verilog modelsim questasim

asked May 25 '19 at 15:17

delkov

301
3
15

0

votes

1 answer

No warning concerning port and assignment in Questa 10.7b

I have a simple code: module test ( input a, output b ); assign a=0; assign b=0; endmodule As you can see a is input, which assigned, thats wrong.. but no warning is shown; my script for compile.do: set work work vlib -type…

verilog modelsim questasim

asked Apr 20 '19 at 20:35

delkov

301
3
15

0

votes

1 answer

Quartus Prime compilation ROM

Hi I am designing a ISA RISCV 32 bits microcontroller and I have organized the ROM in arrays of 8 bits (1 byte), then the out is 32 bit width. Because I need it. rom.txt: (each line is a instruction) 00000011 00100000 00000111 10010011 …

system-verilog riscv quartus rom questasim

asked Dec 23 '18 at 11:45

user8554358

0

votes

0 answers

VHDL Reading text from files, then storing and comparing them to create a Test Bench

I have a text file representing adc values in the integer format from a circuit, which looks like, 0000 0001 0005 3864 2290 1234 . . . 0002 0004 0006 4532 3457 . . . the first 3 integers always represent a header and the subsequent 256 integer…

vhdl fpga modelsim test-bench questasim

asked Dec 09 '18 at 21:29

rooter

5
2

0

votes

2 answers

Set Questa Sim Double-Click Editor

I am trying to get Questa Sim-64 10.7a to open .sv files in Notepad++ when I double-click in the project window. I set the editor command to use Notepad++, so when I use the edit command in the Questa Sim console window it uses Notepad++. That also…

questasim

asked May 17 '18 at 18:17

Jo-Jo Smith

11
5

0

votes

1 answer

Is it possible to fully compile a module and then instantiate it in a testbench separately?

Is it possible to make a fully compiled and standalone version of an RTL module, like a snapshot in Cadence terms, and then later instantiate this compiled module into a testbench? Ultimately, running another compile step to create a final snapshot…

verilog system-verilog cadence questasim synopsys-vcs

asked Apr 27 '18 at 09:03

Ginty

3,483
20
24

0

votes

1 answer

verification using Questasim

I am trying to verify my design in Questasim and the design is in VHDL. I am using Makefile. The command is vcom -93 -work $(work) $(RTL) $(SVTB1) $(SVTB) It is invoking VHDL compiler, but it is not displaying the master_driver signals. Can…

questasim

asked Aug 21 '17 at 11:19

Tsr

11
2

0

votes

1 answer

Parameterized class declaration error in UVM

I'm trying to use a parameterized class extended from uvm_object. class som_util #(int entry_w=2) extends uvm_object; `uvm_object_utils(som_util) "Some other static functions using the parameterized variables" endclass When I run my tests on IUS…

system-verilog modelsim uvm questasim synopsys-vcs

asked Apr 15 '17 at 00:39

seek

41
3

0

votes

1 answer

case statement in property not working for QuestaSim 10.4B

I am trying to write a property with a case statement, straight out of the SystemVerilog 2012 LRM. property p_rate_select (logic [1:0] rate); case (rate) 2'd0 : $rose(i_ffs_rdcount == 1) |=> $fell(o_telem_fifo_ready_n); …

system-verilog uvm system-verilog-assertions questasim

asked Apr 03 '17 at 14:14

noobuntu

903
1
18
42

0

votes

1 answer

$past with an input signal

I want to verify that if an event occurrs, then at “num_ticks” in the past, some signal should have been asserted. As an example, the property I wrote is: property test_past; @(posedge clk) $rose(gnt) |-> $past(req,…

system-verilog uvm questasim system-verilog-assertions

asked Jan 11 '17 at 18:42

noobuntu

903
1
18
42

0

votes

1 answer

uvm_reg peek function takes long time to return

I thought the peek function of uvm_reg returned the value in 0 simulation time. Since I needed this functionality, I implemented all my HDL backdoor access paths. This is the code I am using in my scoreboard while (state == DISABLE) begin …

system-verilog uvm questasim

asked Nov 28 '16 at 20:54

noobuntu

903
1
18
42

0

votes

1 answer

How can I rewrite all signal names to a shorter name?

I'm using QuestaSim/ModelSim and I would like to automatically rewrite the signal names displayed in the waveform. When my testbench starts, a default command loads all top-level signals into the waveform viewer: add wave testharness/* When I…

foreach tcl modelsim waveform questasim

asked Nov 13 '16 at 22:16

Paebbels

15,573
13
70
139

Questions tagged [questasim]