I have this vhdl code :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity avalon_fir_4 is
port (
clk, reset: in std_logic;
-- avalon interface
gcd_address: in std_logic_vector(2 downto 0); -- 3-bit address
gcd_chipselect: in std_logic;
gcd_write: in std_logic;
gcd_writedata: in std_logic_vector(31 downto 0);
gcd_readdata: out std_logic_vector(31 downto 0));
end avalon_fir_4;
architecture arch of avalon_fir_4 is
signal i_coeff_0 : std_logic_vector( 31 downto 0);
signal i_coeff_1 : std_logic_vector( 31 downto 0);
signal i_coeff_2 : std_logic_vector( 31 downto 0);
signal i_coeff_3 : std_logic_vector( 31 downto 0);
-- data input
signal i_data : std_logic_vector( 31 downto 0);
-- filtered data
signal o_data : std_logic_vector( 31 downto 0);
signal wr_en, wr_a, wr_b, wr_c, wr_d, wr_e: std_logic;
type state_type is (idle, count);
signal state_reg, state_next: state_type;
signal c_reg, c_next: unsigned(15 downto 0);
begin
fir_unit: fir_filter_4 port map(clk, reset, i_coeff_0, i_coeff_1, i_coeff_2, i_coeff_3, i_data, o_data);
process (clk, reset)
begin
--if reset=’1’ then
--o_data <= (others=>(others=>'0'));
--data <= (others=>(others=>'0'));
--i_coeff_0 <= (others=>(others=>'0'));
--i_coeff_1 <= (others=>(others=>'0'));
--i_coeff_2 <= (others=>(others=>'0'));
--i_coeff_3 <= (others=>(others=>'0'));
--elsif (clk'event and clk=’1’) then
if wr_a=’1’ then
i_data <= gcd_writedata;
elsif wr_b=’1’ then
i_coeff_0 <= gcd_writedata;
elsif wr_c='1' then
i_coeff_1 <= gcd_writedata;
elsif wr_d='1' then
i_coeff_2 <= gcd_writedata;
elsif wr_e='1' then
i_coeff_3 <= gcd_writedata;
end if;
--end if;
end process;
wr_en <=’1’ when gcd_write=’1’ and gcd_chipselect=’1’ else ’0’;
wr_a <= ’1’ when gcd_address="000" and wr_en=’1’ else ’0’;
wr_b <= ’1’ when gcd_address="001" and wr_en=’1’ else ’0’;
wr_c <= ’1’ when gcd_address="010" and wr_en=’1’ else ’0’;
wr_d <= ’1’ when gcd_address="011" and wr_en=’1’ else ’0’;
wr_e <= ’1’ when gcd_address="100" and wr_en=’1’ else ’0’;
gcd_start <= ’1’ when gcd_address="010" and wr_en=’1’ else ’0’;
gcd_readdata <= r_out when gcd_address="100" else gcd_ready & "000" & x"000" & std_logic_vector(c_reg);
end arch;
compilation crash :
I have tried many ways of writing the vhdl at multiple places without success. What is this error?
