0

I'm trying to do a load "counter", that works counting up the value from my input when load = 1, but i am having problems in the output, it seems to be a trash value on the output. I've used the partial solution from my old question here

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
use IEEE.std_logic_arith.ALL;

ENTITY tot IS
  PORT (
      i_CLK  : IN STD_ULOGIC;
      i_CLR  : IN STD_LOGIC;         
      i_DINL : IN STD_LOGIC ;        
      i_DINK : IN INTEGER;          
      o_DOUTK : OUT INTEGER          
      );     
END tot;

ARCHITECTURE arch_1 OF tot IS
signal w_K : integer;
BEGIN
  PROCESS(i_CLK)
  BEGIN
  IF rising_edge(i_CLK) THEN
      IF (i_CLR = '1') THEN
          w_K <= 0;
      END IF;
      IF (i_DINL = '1') THEN
          w_K <= i_DINK;
          w_K <= w_K +1;
      ELSE
          w_K <= w_K;
      END IF;
  END IF;
  END PROCESS;
o_DOUTK <= w_K;
END arch_1;

My output error:

enter image description here

Why I am having an error if I clear the outputs in the beggining?

Community
  • 1
  • 1
Mutante
  • 278
  • 5
  • 18
  • There's only one projected output waveform (IEEE 1076-2008 14.7.2 Drivers) value for any particular simulation time (including the current simulation time in the case of a implicit “after 0 ns”). Subsequent assignments to the same simulation time will displace the previous assignment in a sequence of statements. See 10.5.2.2 Executing a simple assignment statement and 14.7.5.3 Simulation cycle. Signal assignment doesn't occur during the execution of a process, it's scheduled. For an implicit after 0 ns that means a new value will be available in a delta simulation cycle unless overwritten. –  Jul 04 '16 at 20:02
  • Ok, so If i integrate this with another block, it should work? – Mutante Jul 04 '16 at 20:07
  • The architecture foo in the accepted answer to your previous [question[(http://stackoverflow.com/questions/38044199/integer-to-unsigned-conversion-going-wrong-vhdl-quartus) shows a method of using a single if statement relying on only one assignment to w_K. –  Jul 04 '16 at 20:10
  • integrate what with another block? There's not block statement here other than the elaborated equivalent of the entity and architecture pair. And no, your code doesn't work. –  Jul 04 '16 at 20:11
  • Ok, i understood, this a counter that loads a value, looking at the answer that you gave me in my old question, now i realize that that answer will solve my problem! Sorry about that question, but now i know that the values in the simulation will displace the previous assignment in a sequence of statements! Thanks for the help again! – Mutante Jul 04 '16 at 20:14

0 Answers0