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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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What causes dma_map_page/dma_unmap_page() to take longer time on some hardware?

I've been programming a Linux kernel module for several years for a PCIe device. One of the main feature is to transfer data from the PCIe card to the host memory using DMA. I'm using streaming DMA, i.e. it's the user program that allocates the…
Didier Trosset
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Memcpy Complete After Segfault

I have a PCIe endpoint device connected to the host. The ep's (endpoints) 512MB BAR is mmapped and memcpy is used to transfer data. Memcpy is quite slow (~2.5s). When I don't map all of the BAR (100bytes), but run memcpy for the full 512MB, I get a…
userYou
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how is 'stream ID' or 'iommu specifier' determined in PCIe root complex mode?

This is from Documentation/devicetree/bindings/pci/pci-iommu.txt (linux-5.10.0) PCI root complex ================ Optional properties ------------------- - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier data. The…
Chan Kim
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Atomicity of small PCIE TLP writes

Are there any guarantees about how card to host writes from a PCIe device targeting regular memory are implemented from a software process' perspective, where a single TLP write is fully contained within a single CPU cache-line? I'm wondering about…
nzero
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Multiple PCIe cards: Read device tree properties of the CURRENT PCIe card instance (within a kernel driver)

Question: We are extending a device driver. Our PCIe devices have properties that cannot be auto-detected. In alignment with the Linux kernel maintainers we want to add this properties to the device tree. How can I access, in the driver code, the…
Roelof
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Direct slave DMA transfer from PCIe device to consistent mapped memory without additional memcpy

I am working on improving the throughput of DMA transfers in my custom kernel driver from an FPGA. The current throughput is ~250 Mb/s. The architecture is like this: FPGA connected over PCIe I am allocating a large buffer in RAM using consistent…
Mihai
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Question about Message Signaled Interrupts (MSI) on x86 LAPIC system

Hi I'm writing a kernel and plan to use MSI interrupt for PCI devices. However, I'm also quite confused by the documentations. My understanding about MSI are as follow: From PCI device point of view: Documentations indicate that I need to find…
Shore
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How to configure a specific PCIe devices link speed

I've been experimenting with some UEFI/Kernel code and am working on the various PCI-Express elements. I have obtained the MCFG ACPI table, Enumerated all PCI devices into my own structures and have access to all the devices MMIO regions and the…
JohnHankinson
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Should pci_resource_start(pdev, bar) return same physical address in each boot?

I have noticed pci_resource_start(pdev, bar) returns different address in each boot on the same machine. If it returns a 'physical address', shouldn't it be consistent on same machine? Am I missing something?
keye
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When are TLP packets created in a memory mapped PCIe configuration?

I have an understanding problem when it comes to PCIe connections. In the PCIe interface data is transferred between devices using TLP packets. In a memory mapped configuration if a piece of software wants to send data to a device, then it must…
Emerson Fittipaldi
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Why yield() and cond_resched() do not yield to another thread

Why riffa_driver.c yield() function does not yield to chnl_send() thread ?
kevin
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Get device name from PCIE slot number

I have 4 SSD cards plugged into my system. They show up as /dev/nvme[0-3]n1. Using lspci -vvv I can get the PCIE slot numbers of these 4 cards. But how to match the PCIE slot number with the device name? For example one of the cards has the slot…
Mia Dawson
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Detect transaction from PCIe endpoint to host memory in Linux

I'm building an FPGA design in which some devices (CPU, UART, GPIO controller) are connected to an AXI4 bus. The AXI4 bus is connected to the host via Xilinx' "AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.6 LogiCORE IP", which acts as a bridge.…
Thomas Grass
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Intel Z370 - SMBus on PCIe

I have here a card that fits in an PCIe slot, with some SMBus controllable chips on it. The card is self layouted and works fine in some older mainboard. In a newer mainboard (ASUS PRIME Z370-A) it is not working. The card is not using the PCIe…
Hans Müller
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FPGA and PCIe Swich

We are planning to develop a stand-alone board with one Xilinx FPGA that needs to communicate with several onboard modules. Some of these modules have a PCIe interface and thus working as a PCIe Endpoint. We don't have many experience in this field…
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