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Questions tagged [memory-barriers]

A memory barrier is a special processor instruction that imposes restrictions on the order in which memory accesses become visible to other processors/cores in a multi-processor or multi-core system.

This tag is for questions that are about the consequences of memory barriers, or whether or not a memory barrier is needed.

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Is function call an effective memory barrier for modern platforms?

In a codebase I reviewed, I found the following idiom. void notify(struct actor_t act) { write(act.pipe, "M", 1); } // thread A sending data to thread B void send(byte *data) { global.data = data; notify(threadB); } // in thread B event…
mikebloch
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How do I Understand Read Memory Barriers and Volatile

Some languages provide a volatile modifier that is described as performing a "read memory barrier" prior to reading the memory that backs a variable. A read memory barrier is commonly described as a way to ensure that the CPU has performed the reads…
Jason Kresowaty
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Does it make any sense to use the LFENCE instruction on x86/x86_64 processors?

Often in internet I find that LFENCE makes no sense in processors x86, ie it does nothing , so instead MFENCE we can absolutely painless to use SFENCE, because MFENCE = SFENCE + LFENCE = SFENCE + NOP = SFENCE. But if LFENCE does not make sense, then…
Alex
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Why we need Thread.MemoryBarrier()?

In "C# 4 in a Nutshell", the author shows that this class can write 0 sometimes without MemoryBarrier, though I can't reproduce in my Core2Duo: public class Foo { int _answer; bool _complete; public void A() { _answer = 123; …
Felipe Pessoto
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Are mutex lock functions sufficient without volatile?

A coworker and I write software for a variety of platforms running on x86, x64, Itanium, PowerPC, and other 10 year old server CPUs. We just had a discussion about whether mutex functions such as pthread_mutex_lock() ... pthread_mutex_unlock() are…
David
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Why do I need a memory barrier?

C# 4 in a Nutshell (highly recommended btw) uses the following code to demonstrate the concept of MemoryBarrier (assuming A and B were run on different threads): class Foo{ int _answer; bool complete; void A(){ _answer = 123; …
hackerhasid
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Atomicity of loads and stores on x86

8.1.2 Bus Locking Intel 64 and IA-32 processors provide a LOCK# signal that is asserted automatically during certain critical memory operations to lock the system bus or equivalent link. While this output signal is asserted, requests from other…
Gilgamesz
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Behavior of memory barrier in Java

After reading more blogs/articles etc, I am now really confused about the behavior of load/store before/after memory barrier. Following are 2 quotes from Doug Lea in one of his clarification article about JMM, which are both very…
asticx
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When is a compiler-only memory barrier (such as std::atomic_signal_fence) useful?

The notion of a compiler fence often comes up when I'm reading about memory models, barriers, ordering, atomics, etc., but normally it's in the context of also being paired with a CPU fence, as one would expect. Occasionally, however, I read about…
etherice
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Can atomics suffer spurious stores?

In C++, can atomics suffer spurious stores? For example, suppose that m and n are atomics and that m = 5 initially. In thread 1, m += 2; In thread 2, n = m; Result: the final value of n should be either 5 or 7, right? But could it…
thb
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Does std::mutex create a fence?

If I lock a std::mutex will I always get a memory fence? I am unsure if it implies or enforces you to get the fence. Update: Found this reference following up on RMF's comments. Multithreaded programming and memory visibility
Tom Kerr
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Memory fences: acquire/load and release/store

My understanding of std::memory_order_acquire and std::memory_order_release is as follows: Acquire means that no memory accesses which appear after the acquire fence can be reordered to before the fence. Release means that no memory accesses which…
Siler
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Does a memory barrier ensure that the cache coherence has been completed?

Say I have two threads that manipulate the global variable x. Each thread (or each core I suppose) will have a cached copy of x. Now say that Thread A executes the following instructions: set x to 5 some other instruction Now when set x to 5 is…
Christopher
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Should thread-safe class have a memory barrier at the end of its constructor?

When implementing a class intended to be thread-safe, should I include a memory barrier at the end of its constructor, in order to ensure that any internal structures have completed being initialized before they can be accessed? Or is it the…
Douglas
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C++ Memory Barriers for Atomics

I'm a newbie when it comes to this. Could anyone provide a simplified explanation of the differences between the following memory barriers? The windows MemoryBarrier(); The fence _mm_mfence(); The inline assembly asm volatile ("" : : :…
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