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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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Porting PCIe driver from Linux to FreeBSD

I have a fairly large PCIe driver written on/for Linux, now I need to port it on FreeBSD. I don't yet know the BSD version, but I think at this point it's irrelevant, as I'd like to understand in general what major items will have to be modified…
Mark
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How PCIe NIC works and How it communicates with hosts?

I am using intel i210 1G NIC card with my intel i7 PC, I want to know how this NIC communicate with the host without configuring anything out of the box. What NIC exports as a PCIe device to host, How this information is used by the host pci and…
Jagdish
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Linux Network Driver MSI Interrupt Issue

I am attempting to create a network driver for custom hardware. I am targeting a Xilinx Zync-7000 FPGA device. My issue is the software handling of the MSI interrupt on the CPU side. The problem I have is when the interrupt is fired on the PCIe…
ThisGuy
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GPUDirect Peer 2 peer using PCIe bus: If I need to access too much data on other GPU, will it not result in deadlocks?

I have simulation program which requires a lot of data. I load the data in the GPUs for calculation and there is a lot of dependency in the data. Since 1 GPU was not enough for the data, so I upgraded it to 2 GPUs. but the limitation was, if I…
Roshan
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Atomic operations in CUDA kernels on mapped pinned host memory: to do or not to do?

In CUDA programming guide it is stated that atomic operations on mapped pinned host memory "are not atomic from the point of view of the host or other devices." What I get from this sentence is that if the host memory region is accessed only by one…
Farzad
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How to force kernel to re-read/re-initialize PCI device IDs?

My machine (running Linux kernel 3.2.38) on boot has wrong subsystem IDs (sub-device and sub-vendor IDs) of a PCI device. If I then physically unplug and re-plug the PCI device while the system is still up (i.e., hot-plug), it gets the correct…
Jahanzeb Farooq
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DMA over PCIe to other device

I am trying to access the DMA address in a NIC directly from another PCIe device in Linux. Specifically, I am trying to read that from an NVIDIA GPU to bypass the CPU all together. I have researched for zero-copy networking and DMA to userspace…
jrk0414
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What is the difference between pci_enable_device_mem and pci_enable_device?

What is the difference between pci_enable_device_mem and pci_enable_device? In ixgbe pf driver uses pci_enable_device_mem and vf driver uses pci_enable_device.
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Determine what (if any) PCI devices are plugged into motherboard PCI(e) slots

I am writing a program in C# to perform a hardware audit across many Windows XP workstations. I need to determine which PCI devices are actual cards connected via a motherboard slot - NOT onboard devices that also use the PCI buses (built into the…
Bosco
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mmap() slower than write() copy_form_user(), why?

I need to transfer big blocks of data (~6MB) to my driver from user space. In the driver, I allocate 2 3MB chunks per block using pci_alloc_consistent(). I then mmap() each block (i.e. 2 chunks) to a single vma using vm_insert_page(). This allows…
dczulak
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Interfacing a linux device driver with dummy PCI device

I have a user space program that simulates a PCI device. I have downloaded the nvme linux device driver that interacts with the PCI device using the NVMe standard. I have to verify that my userspace program is compatible with the standard. The…
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Is it possible to write to multiple devices that use different PCIe lanes on the same PCIe slot?

I am writing a Linux device driver which supports multiple devices. I have a x8 PCIe card with 4 of these devices on it. Each runs through a PCIe switch and gets 2 PCIe lanes. Is there a way to have the driver write to multiple lanes at the same…
Chris
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Can I put a PCI-E 3.0 x16 gpu in a PCI-E 1.0 x16 slot?

I have an old motherboard the Asus P5K Deluxe. I need to change my current GPU ( NVIDIA 8800 GTX ) but all new GPU's seem to use a PCI-E 3.0 slot. Are the 3.0 backwards-compatible with the 1.0 slots? Are there any adapters? I have been googling this…
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PCIe Gen 5.0 specification register figure drawings - dotted lines Vs solid lines

above is an example of a figure from PCIe Gen5.0 specification. here some bit locations are marked with dotted green line Vs some are marked with solid black lines. While spec defines all bit fields and all figures, i could not find purpose behind…
ankit patel
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Failed to read pci csr via mmap using uint64_t pointer

I'm trying to reading PCI CSR (Configuration Space Register) on my system via open,mmap /dev/mem. I met some problems when using 8 byte length reading Here is the minimal working example of my code #include #include #include…
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