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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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DMA PCIe read transfer from PC to FPGA

I'm trying to get DMA transfer working between an FPGA and an x86_64 Linux machine. On the PC side I'm doing this initialization: //driver probe ... pci_set_master(dev); //set endpoint as master result = pci_set_dma_mask(dev, 0xffffffffffffffff);…
Cpu86
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How does a PCIe device appear bootable to the BIOS/UEFI?

I have an Intel based host system with a PCIe daughter card that my company has designed. We are able to have it be enumerated to allow memory to be shared with the intel processor. I am looking to make the daughter card memory space, accessible…
penguin4hire
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How to access PCIe configuration space? (ECAM)

In order to access PCI Configuration Space, I/O port address 0xCF8, 0xCFC is used according to various articles. mov eax, dword 0x80000000 mov dx, word 0x0CF8 out dx, eax mov dx, word 0x0CFC in eax, dx The value of eax in the above code was…
YoonSeok OH
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Understanding "nvidia-smi topo -m" output

In order to leverage the GPUs on a system, I'd like to be able to draw a block diagram and understand the connections represented by "nvidia-smi topo -m" output. Here is an example output: Can someone provide a system level block diagram of this? …
user3731622
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How to access pci express configuration space via MMIO?

I am new to PCI express, I want to read/write into PCI Express configuration space via MMIO addresses. I know how port mapped IO read/write into PCI express config space via 0xCFC and 0xCF8 port addresses(on x86). I also wrote a sample linux kernel…
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Generating a 64-byte read PCIe TLP from an x86 CPU

When writing data to a PCIe device, it is possible to use a write-combining mapping to hint the CPU that it should generate 64-byte TLPs towards the device. Is it possible to do something similar for reads? Somehow hint the CPU to read an entire…
haggai_e
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pci_enable_device() fails after remove/rescan

I have here Linux 4.4 (I used to work on an older kernel which failed in the same way) with a PCIe connected FPGA device and a driver for it which are both of my own design. These have been working well under normal conditions, but now I try to make…
Andreas Bombe
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How does PCI/PCIe devices init/register themselves in the Linux kernel?

When the kernel starts up, the PCI subsystem creates a pci_bus for each physical PCI bus, then the pci_bus is added to pci_root_buses(with PCI configuration). But the PCI device driver registers drivers by pci_register_driver, and it adds PCI driver…
hooao
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How can a PCIe card dma data into CPU ram?

This is in reference to this answer given to a similar dma/pci question. I gathered from this answer that the PC does not have a dma capable of transferring data to/from a PCI card, and that the PCI card must provide the dma capabilites. I have…
tomcat
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Do I need to "enable" a PCIe memory region in a Linux 3.12 driver?

I have code, called from the probe() function of my PCIe driver (loosely based on this post): EDIT: Based on Andreas Bombe's response, I changed the code to use pci_iomap(), but I'm still experience the system hang static my_pci_dev pci_dev; /*…
Jamie
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PCIe JTAG for (re)programming a PCIe board

I noticed that the PCI bus has the JTAG wires (i.e. TCK TDI TDO etc.): is there any way to use that JTAG for re-programming an fpga based PCIe device? (supposing that the fpga's JTAG is connected to the PCI wires). thanks Michele EDIT: since I see…
Michele
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What are the PCIe operations involved in Infiniband verbs?

Here are some specifics. When a process calls ibv_post_send(), what happens at the PCI interface to the HCA? Is the WQE encapsulated inside the PCIe doorbell and written via Programmed IO? Or is the WQE fetched in a separate DMA read by the…
Anuj Kalia
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How does the CPU know the PCI adress-space

I understand that PCI and PCIe devices can be configured by the CPU (via code in the BIOS or OS) to respond to certain physical memory addresses by writing to specific areas of the device's configuration space. In fact the Linux kernel has quite the…
Lifesworder
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CUDA - how much slower is transferring over PCI-E?

If I transfer a single byte from a CUDA kernel to PCI-E to the host (zero-copy memory), how much is it slow compared to transferring something like 200 Megabytes? What I would like to know, since I know that transferring over PCI-E is slow for a…
Marco A.
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Prefetch from MMIO?

Is it possible to issue a prefetch for an address backed by an MMIO region in a PCIe BAR (and mapped via either UC or WC page table entries)? I am currently issuing a load for this address which causes the hyperthread to stall for quite some time.…
Jack Humphries
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