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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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How to get IRQ Pins in PCI

I was creating some drivers and I found my self stuck in the IRQ Pins, my kernel uses IOAPIC and I don't know how this interrupt mechanism (IRQ Pins) works and how to get them and use them. Can anyone give a detailled answer on how to use them to…
git_lk1
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What does accuracy means in PCIe local clock?

In the receiver side of the physical layer's logic block, the local clock is accurate to +/- 300 ppm. Can anyone explain about this in details please?!
Roronoa_Zoro
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Enable CPU option from OS not in BIOS

I would like to know if there is any way to enable a specific feature in the CPU, if that feature is not given in the BIOS. For example, i have Xeon E5-2680 V2, according to the data sheet this processor supports NTB on PCIe Port3a. But this NTB…
user777304
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why there is a shift from parallel to serial bus in pcie?

There is parallel bus for pci and serial bus for pcie. Why parallel bus cannot be used for pcie but are using serial bus? why there is shift to serial bus for pcie?
Pooja Balachandran
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How to parse PCI addresses with regex?

I'm trying to find a reliable regex pattern for parsing a PCI address from a listing in sysfs. For example: s = " # total 0 # drwxr-xr-x 7 root root 0 Mar 22 21:30 . # drwxr-xr-x 121 root root 0 Mar 22 21:27 .. # drwxr-xr-x 2 root root …
tarabyte
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How a pc host issue long pcie read/write burst to my device?

I have a pcie board with a segment of memory which is mapped to system address space. The memory controller can accept long burst read or write request. In the host program, when I use for loop to read or write the memory, will the host generate…
Chao Xiang
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Samsung NVMe 980 PRO and Alfais 4390 M.2 Nvme Ssd Ngff To Pcie 3.0 X16 compatibility

Dear Friends I need help. Is the following combination compatible? What will be the maximum write and read speed I will get, AS MegaBytes? I will be glad to hear for your comments. 1- Samsung NVMe 980 PRO 2- Alfais 4390 M.2 Nvme Ssd Ngff To Pcie 3.0…
Aydin Secer
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Is it possible to connect a pciE slot to one of many Root Complexes

Is it possible to connect a pciE slot to one of many Root Complexes, as if the device network is a fully connected graph Let me give an example. Number of Sockets - 1 Number of CPUs per Socket - 2 (Cpu0 & Cpu1) Connect two Gpus Gpu1 and Gpu2 Per…
saidasa
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SuperMicro compatible with ZC706 Xilinx Board

We are looking to buy a SuperMicro machine to install the Xilinx ZC706 board on it for a specific project. We wanted to make sure which machine is and which intel processor family ( Haswell or Broadwell ) is compatible with the board? We had a bad…
saman
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Why does lspci lists pcie devices?

When I do lspci I can see my nvme ssds. Why is that? Aren't PCI buses supposed to be separate from PCIe buses?
Shawn Li
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CUDA - GB/s for PCI-E vs Gbps for memory clock speed for GPUs

I'm astounded at PCI-E 3.0 speed: ~16 GB/s (gigabytes per second) against top gamma GPUs memory clock speed (a Titan X lists ~10 Gbps i.e. giga-bits per second) So we have PCI-E 3.0 16 GB/s Titan X ~1 GB/s So the question is: why is there…
Dean
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How are PCIe lanes distributed between CPU and peripherals

I'm about to build a desktop computer and I'm trying to understand how are this PCIe lanes distributed. The goal is being able to calculate how many lanes do I need for a certain setup. I'm looking at the Asus Z170-P motherboard, which according the…
Rock Storm
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PCI Express how to connect read write using C#

i need any documentation code that explain to me how to read write to Express Port using c#
Khalid Osama
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how long does it take to write a PCIE to Serial windows driver with zero knowledge?

I need to write a serial driver for PCIE with interrupts, contigious buffer DMA and simple read/write requests from PC to PCIE. I have no knowledge on drivers and small knowledge on PC architecture. How long should it take on average?
Menderft
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