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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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MAC Address not changing after writing to Base Address Register 0

I have a problem and I honestly have no idea where the problem is. I use an Intel Ethernet Controller and my objective is to change the MAC Address of that Controller. What I allready did is mapping the BAR0 to virtual address space and changing the…
A.Z.
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who fills the device configuration space of pci?

I want to know who fills the configuration space of a particular device of PCI at the first place when a new device is connected to the PCI bus. I know both bios and operating system can configure the PCI space but who gives the information of the…
karan sharma
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How to benchmark PCIe and DMA?

I am using Intel x520 and x540 dual port NIC attached to Dell PowerEdge server. All NIC ports can work at 10Gbps, hence total 40 Gbps. The system has 2 sockets containing Xeon E5-2640 v3 CPU(Haswell Microarchitecture). There are many problems I am…
A-B
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PCI express flow control credits

I am reading PCI express documentation and have a question connected with “TLP Flow control Credits”. This is what I understood: as PCI express does not have sideband signal e.g. IRDY, TRDT, RBF, is uses flow control credit model. There are…
haykp
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Can Power8 use atomic operations to communicate with ASIC/FPGA connected by PCI Express?

As known, Power8 supports Coherent Accelerator Processor Interface (CAPI): https://www.nextplatform.com/2015/06/22/the-secret-of-power8-capi-is-addressing/ Hardware Managed Cache Coherence Enables the accelerator to participate in “Locks” as a…
Alex
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Sending a PCIe message

How to send a PCIe message(specifically VDMs - Vendor Defined Messages) from a host application/driver? Is there any windows API to do the same, like there are APIs for Memory R/W or I/O R/W ? I could see Teledyne tool having support for PCIe VDM…
nerd
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PCIe Integrated Endpoint for Ultrascale 32-bit register interface issues

I am having some intermittent issues with reading registers from logic connected to the PCIe Integrated endpoint. I am using a virtex ultrascale board and the register bus is mapped to bar 0. I do 32-bit reads and writes most of the time with no…
user310153
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MSI Interrupts working, but MSI-X interrupts not triggered - Interrupt remapping disabled

I am writing a linux driver that talks to an Altera FPGA over PCIe. The FPGA supports both MSI and MSIx interrupts. In general, MSI interrupts appear to be working okay, however, MSIx interrupts appear to work on some computers and not others.…
dylan3287
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Two-way communication to PCIe device via /dev/mem in Linux user-space?

Pretty sure I already know the answer to this question since there are related questions on SO already (here, here, and here,, and this was useful),,, but I wanted to be absolutely sure before I dive into kernel-space driver land (never been there…
yano
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NdisMGetBusData function returns zero

I'm trying to develop NDIS6.0 based mini-port driver on WEC7 (Windows Embedded Compact 7) for a PCIe network card. In MPInitialize function when I try to read PCI config space using function NdisMGetBusData, It is returning zero. From documentation,…
Keshava GN
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PCIe Legacy Interrupts for Integrated GbE Controller

I am writing ethernet drivers for GbE Controller for Autosar which is a pcie device(20) for intel x86 based platform, So far I have been able to configure IOAPIC for timer and GPIO interrupts but I am unable to receive PCIe legacy interrupts on…
Waleed Abbasi
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How to configure PCI Express hard ip in Stratix IV?

I want to use PCI Express for my upcoming project. So before working for my project I want to do some basic exprements with PCI express. I tried PCI Express reference for stratic IV and it was succesful. As a next step I want to either modify the…
teenu
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Need Help to Develop Linux PCIe Driver using DMA Concept

Currently, I am developing my Own Video Frame Buffer Driver with help of Linux PCIe and Virtual Frame Buffer Driver. My Custom Driver works fine on 720X480P Video Resolution but getting some slow on 720P Video Resolution. I have just directly mapped…
Ritesh Prajapati
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How do I calculate PCIe 1x, 2.0, 3.0, speeds properly?

I am honestly very lost with the speeds calculations of PCIe devices. I can understand the 33MHz - 66MHz clocks of PCI and PCI-X devices, but PCIe confuses me. Could anyone explain how to calculate the transfer speeds of PCIe?
Space Ghost
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pci device info access in linux from userspace

I want to access the pci device tree information from user space programatically. Like the root complex and the devices connected to it. How can I do it please let me know. Regards, Pradeep
Pradeep Jagadeesh
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