Stack Overflow
Stack Overflow

Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

449 questions
0
votes
1 answer

Pcie 1.1 device is not detected on a pcie gen 3 slot

My PC is running in Ubuntu 12.04 LTS with kernel version 3.11.0-23. The link below is my PC model: http://www.villman.com/Product-Detail/HP_Pavilion_500_232d I inserted a x4 pcie 1.1 device on the x16 PCIE 3.0 slot. When I do lspci, my device is not…
Fedemar
  • 1
  • 1
0
votes
1 answer

Capture PCI-Express wheh it is connected and than emulate in system

Is there any way to capture device state when it's connected and than emulate it in Windows? I bought some PCI Express devices that need to be present in slots to make software working. But I have only one slot and software not fully works,…
Wind
  • 59
  • 2
  • 10
0
votes
2 answers

If I have only the physical address of device buffer (PCIe), how can I map this buffer to user-space?

If I have only the physical address of the memory buffer to which is mapped the device buffer via the PCI-Express BAR (Base Address Register), how can I map this buffer to user-space? For example, how does usually the code should look like in…
Alex
  • 12,578
  • 15
  • 99
  • 195
0
votes
1 answer

Can I send via Infiniband data without using a DMA-controller?

Can I send data via Infiniband without using a DMA-controller and what the smallest size of packages can I send? That is, can I directly access to the memory of the remote CPU2-RAM from current CPU1-Core by using simple pointer (i.e. only x86-asm:…
Alex
  • 12,578
  • 15
  • 99
  • 195
0
votes
1 answer

unable to set value of latency_timer register of PCI configuration space

I am trying to set latency timer value of my Intel PCI card using following command sudo setpci -d '8086:0100' latency_timer=01 But when I read the value of this register back it is unchanged and shows previous value. I am using following command…
Waqas
  • 191
  • 3
  • 4
  • 13
0
votes
2 answers

PCI expansion ROM header Entry point for INIT function

As indicated in section 6.3.3.1. ROM Header Extensions (PCI Local Bus Specification v2.3), offset 0x3h is "Entry point for INIT function. POST does a FAR CALL to this location.", this field's length is 3 bytes. I have a PCI Rom image which length…
Dien Nguyen
  • 2,019
  • 6
  • 30
  • 37
0
votes
2 answers

DMA engine is not responding correctly on PowerPC linux

DMA engine is not responding correctly on PowerPC linux. When my PCIe device sends a read / write request to host, timeout happens. I have 1GB of RAM at lower address range. I have called the following…
user2651022
  • 11
  • 2
0
votes
1 answer

What's is the maximal size of single Memwr TLP(BAR ACCESS) from the root complex to endpoint on a X86 platform?

What's is the maximal size of single Memwr TLP(BAR ACCESS) from the root complex to endpoint on a X86 platform? The setup of my system is that there is a PCIe endpoint device plugged into an X86 PC, and the bar0 size of this device is 1 MBytes, and …
TiisCool
  • 3
  • 1
  • 3
0
votes
1 answer

PCIe read write within ISR

I'm modifying a linux PCIe driver to work with altera FPGA PCIe core. Inside my driver code, I'do pci_set_master(dev) to make the PCIe read write working. I'm using altera SG-DMA to do PCIe transfer instead of using ARM DMA. I need to write enable…
Shahril
  • 65
  • 1
  • 7
0
votes
2 answers

Get VGA BUS type via VB.net

How do get VGA BUS type (AGP, PCI, PCI-e...) via VB.net? This return what videocards in computer: SELECT Name, PNPDeviceID FROM Win32_VideoController How can I get the bus type from these video cards to have PCI or PCI-e or AGP connected to…
Zserigta
  • 52
  • 9
0
votes
1 answer

PCIe MSI Address register

If i understand correctly MSI host driver should write it target MSI address to relative remote register. How can i get MSI Address register,MSI Config register and so on? Could you explain me this issue?
Ilya Shcherbak
  • 131
  • 2
  • 11
0
votes
2 answers

Testing PCI Interface on FPGA

My boss has given a code for testing PCI express on an Altera board. The code consist of several c code files having instructions such as reading Bios, setting some registers, writing to buffers etc. My job at present is to see the functionality of…
gpuguy
  • 4,607
  • 17
  • 67
  • 125
-1
votes
0 answers

Error compiling/running C PCI-e API for Windows 10

I was recently assigned a job in a programming language that I don't usually use on a daily basis and whose last use probably dates back to university studies: i'm talking about C! I have to modify a program to communicate through PCI-e, the…
Lubron
  • 35
  • 2
  • 15
-1
votes
0 answers

How to Simulate PCIe Design Using BFMs? Intel PCIe_DDR Design

I am trying to simulate the reference design (PCIe_DDR4) on Terasic DE5a-Net DDR4 edition board. I want to simulate this and confirm meaningful DDR4 read/writes in ModelSim. Referring to Intel Documentation :…
baggins6000
  • 9
-1
votes
1 answer

How to obtain the PCIe ECAM base address under Linux?

Is there a way to obtain the physical base address of PCIe ECAM space under Linux (e.g., via sysfs or dmesg)? My intention is to use devmem2 to exam the ECAM space, and compare the result with lspci -x. I am assuming that ECAM space can be accessed…
bruin
  • 979
  • 1
  • 10
  • 30
1 2 3
…
29
30