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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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How to guarantee all DMA data write into ram when getting msi interrupt?

There are some questions that make me confused: Msi interrupt is a memory write request. Can msi ensure that all DMA data have been written into ram? or only ensure that the data has been transferred completely on pci bridge? If msi interrupt only…
JoyC
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PCIe Understanding

As this domain is new for me, I have some confusions understanding PCIe. I was previously working on some protocols like I2c,spi,uart,can and most of these protocols have well defined docs(a max of 300 pages). In almost all these protocols…
AlphaGoku
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How does PCIe endpoint remembers its Bus Device Function Number?

How does the PCIe endpoint claim the configuration transaction since there is no register (in Type0 config space) defined by PCIe specification which holds the Bus Device and Function number.
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How to properly disable a PCIe device?

I am writing a device driver in linux for PCIe endpoint implemented on Xilinx UltrascaleMPSoC FPGA part. I have implemented the remove function correctly. I connect my device using an adapter to my PC, turn on device, enable its Endpoint and then…
HarishAG
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Question on PCI Express(PCIe) configuration space access on VirtualBox

Hi I'm trying to access the PCIe configuration space with MMIO method on a kernel base. Before I drop my question, my platform is Windows 10, VirtualBox 6.0.10. My virtual machine set as default except the following: chipset choosed ICH9 Core…
Shore
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Why do my PCI-e I/O register reads appear to be cached?

I have a PCI-e hardware device that has a number of registers that I want to read from and write to. However, when I read a register, I will get a value from a previous read (the first read returns 0xFFFFFFFF). I'm using pci_iomap() to get the…
Gil Glass
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How do PCIe error messages find it's root port?

Simple question, but I cannot find the answer in the spec nor in the mindshare book. MSI has it's capabilities that tell the device where to send their interrupt messages. Is there a similar register telling the device where to send the error…
Pyjong
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How is data transferred from memory to PCIe cards?

My question is about data transfer between a PCIe peripherial and system memory. Example: Suppose we need to send a big chunk of data ( stored in system memory ) over an Ethernet network. How will it usually be done ? Will the Ethernet card's…
shaiko
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How can I access or get data(bit stream) in PCI configuration register(space) in Windows platform

I need to read data in PCI configuration register. PCI configuraion registers are allocated in memory because PCI architecture is memory mapped I/O. So, I want to read the data in configuration register or space in Windows OS. How can I get this…
JS Kim
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PCIe TLP write packet address only 31:2 bits

Let's take a sample write packet : Suppose that the CPU wrote the value 0x12345678 to the physical address 0xfdaff040 using 32-bit addressing This example is from this site (I didn't understand the explanations in the original post) Why…
mohamed azaiez
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Is it possible to track display driver memory accesses over PCIe?

Our team wishes to write a performance measuring tool with focus on GPUGPU In order to understand if a particular app is compute-bound or memory-bound we would like to track Graphic card's memory accesses without sticking to any compute API Is it…
Dmitry
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How does BIOS determine the type of device during PCI Express Bus Enumeration?

During the PCI Express Bus enumeration, How does BIOS figure out the type of the device i.e. whether its a PCI or PCI express device?
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Mapping PCIe BAR regions of size greater than 4MB in Xilinx Vivado

We are developing a system with a custom processor, Microblaze and some peripherals in VC709 FPGA using Xilinx Vivado. We are using two 'PCIe : BARs' in 'AXI Bridge for PCI express gen 3'. The changes we make in the block configuration of the PCI…
vineeshvs
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Multiple entries of PCIe address range in /proc/mem log

I use dma_alloc_coherent() in my custom driver to get both virtual and bus addresses. res->KernelAddress = (u64)dma_alloc_coherent( &DevExt->pdev->dev, size, &res->BusAddress, GFP_ATOMIC ); When printing (%llx) the bus address (res->BusAddress), I…
PBang
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PCIe Problem -- Why pciehp gives contradictory log info

I am running fio jobs on my NVMe SSD and hotplug it then. The platform is hot-pluggable and the system is Centos 7.0.Several seconds after my plug-out, the system encounters a crash and gives these print info: ================ [ 1026.468414]…
Leo Erzhuo Chen
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