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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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How to add pciutils package in yocto AGL?

I have built Yocto AGL(6.0.0) image for RCar-salvator-xs board and flashed its hyperflash memory. Now, I want to perform PCIe related investigation, for that I want to use lspci command. But, After ligging in as a root in flashed AGL image and…
user10561367
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Multiple Message Signal Interrupt (MSI) support on x86 arch for Virtualbox

I have a custom PCIe endpoint (generic endpoint supporting basic capabilities) and that sets Multiple MSI capability IRQ vectors to 16. But as I run the x86_64 bit guest ubuntu desktop OS which has the PCIe host controller that configures MSI Enable…
Adit Ya
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PCIe PIC_INTERRUPT_PIN (0x3c) is 0

I write my pcie driver for a custom board. I am going to use an interrupt. if(request_irq(dev->irq, pci_dma_irq, IRQF_SHARED | IRQF_TRIGGER_HIGH, "PCIe sol_dma", dev)){ unit_err("request irq %d\n", dev->irq); ret = 1; } #…
laplace11235
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Using memcpy on mmap'ed region crashes, a for loop does not

I have an NVIDIA Tegra TK1 processor module on a carrier board with a PCI-e slot connecting to it. In that PCIe slot is an FPGA board which exposes some registers and a 64K memory area via PCIe. On the ARM CPU of the Tegra board, a minimal Linux…
sktpin
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How does a Linux distribution affect the kernel behavior

This might be obvious for some but not to me so I'll ask =) I'm having an issue that I have build an embedded Linux stack for some piece of hardware (NVidia TX2 + ConnectTech Astro carrier). I use a PCIe card from EPIX If I use Ubuntu's official…
Damien LEFEVRE
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How to determine PCIe slot number from dmesg error message?

I have a Linux system that contains several PCIe cards. dmesg indicates that one of the cards is generating an error: [ 3970.385387] pcieport 0000:00:02.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, id=0010(Transmitter ID) […
DavidA
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What can be a reason of PCI MMIO read data delay?

Our team is currently working on custom device. There is Cyclone V board with COM Express amd64-based PC plugged into it. This board works as PCIe native endpoint. It switches on first, then it switches PC on. PC has linux running on it with kernel…
yurimz
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how to Access monitor information from the Video RAM and display it on GUI using c#

I am using Xilinx Spartans SP605 board to access pciexpress through PCI bus. For that i am using JUNGO tool( Windriver) for generating the drivers for the device used and then accessing the PCIexpress card by performing read and write operation…
Nawazish Ahmed
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In which file enumeration of PCIe devices is located in Linux kernel for ARM based system?

I am working to develop PCIe drivers for a custom ARM based platform. As a starting point I have started to look into Linux kernel 4.15.9 code. I am unable to locate the relevant PCIe driver files. In particular I am interested in PCIe device…
tue2017
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PCIe: how to transfer metadata with minimum overheads

Lets say I have an existing PCIe system - say a host CPU connected to a PCIe NIC card. I would like to transfer some metadata between host and device - say some debug information that I want to transfer on a per packet basis. I would like to avoid…
user9407884
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Should we read BAR type before writing all F's to the BAR or before that?

I am working on a PCI express driver. I am reading the BAR of the root complex device to find the memory type and the size it requires. I know that to find the size of memory we need to write all F's to the BAR and read it back, clear the last 4…
Amna
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Unable to access specific PCIe device's memory-mapped region

I am working on an x86-based 64-bit system. The device in question is an eMMC controller, that has 64-bit memory-mapped regions. I am trying to access first region through the address pointed to by the BAR, but I can only read 0xffffffff's…
Hamzahfrq
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PCIe cards interfere with each others function

Hello Good People of the Internet! First time asking... I have a modern PC running Fedora 24 with a real-time patch (CCRMA audio tools) with an ASUS Essence STX II sterio sound card installed on PCIe. With it we run a playback/capture application.…
peso
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Is there any method of reading and writing more than 1 DW from the user-space of PCI device?

Is there any method of reading and writing more than 1 DW from the user-space of PCI device? I am currently using https://github.com/numato-viya/pcimem this code for accessing the data from the user space of the PCI device but the limitation of this…
Hamayoun Ahmad
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Using DMA to communicatte PCIe

Xilinx corp. released some programs for working with its DMA PCIe IPcore which is available here. Whitin these programs, there are some programs that performs C2H or vise versa high speed operations. Is it basically using DMA in host side or…
Mahdi
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