How do PCIe error messages find it's root port?

Question

Simple question, but I cannot find the answer in the spec nor in the mindshare book. MSI has it's capabilities that tell the device where to send their interrupt messages. Is there a similar register telling the device where to send the error messages? Is there some dedicated address/bdf that would have some sort of "pass upstream" meaning? Does it always use all zeroes for destination and root port picks it up on the way?

Thanks

What kind of error messages specifically are you asking about? — prl, Jul 15 '19 at 22:09

score 1 · Accepted Answer · answered Jul 15 '19 at 22:09

1

Section 2.2.4 of the PCIe spec (rev 4.0) describes address- and ID-based routing. Memory reads and writes are routed based on the memory address. Completions are routed by ID.

Section 2.2.8 describes the routing of messages, including error messages. In particular, see Table 2-17 on page 105, section 2.2.8.3, and Table 2-21. Table 2-21 shows that the Routing field for Error Signaling Messages is always 0, indicating that they are routed toward the Root Complex.

The MSI capabilities don't have any special information about PCIe routing. An MSI is performed using a memory write transaction, so it is routed by address.

answered Jul 15 '19 at 22:09

prl

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Presumably upstream completions are also routed toward the Root Complex, rather than by ID, but I didn't find anything in the spec that says that. – prl Jul 15 '19 at 22:10
I read the parts you mentioned, that makes perfect sense, thank you very much. But I still can't wrap my head around your comment. Could you elaborate please? – Pyjong Jul 18 '19 at 10:42
I think my comment was wrong, but here's what I was thinking: A memory read request from a device carries the requester ID of the device and the memory address being accessed. The request is routed by address to the appropriate completer. The read completion carries the requester ID of the device and is routed by ID to be sent back to the device. A memory read request from the CPU to a device (an MMIO access) is routed by the memory address to the device. I'm not sure what requester ID is carried in the request, which would be used to route the completion back to the requester. – prl Jul 19 '19 at 01:40
After some more reading, I'm still not sure, but I guess the read request (and the completion) contain the requester ID of the root port, so the completion is routed by ID back to the root port. – prl Jul 19 '19 at 01:40

How do PCIe error messages find it's root port?

1 Answers1