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Questions tagged [pci-e]

PCI-Express (PCIe) is a peer 2 peer interconnect which is based on PCI and PCI-X. Newest generation is gen 5.0. PCIe is maintained and developed by PCI-SIG.

Versions

  • PCIe Gen1 -- Released in 2003, PCIe Gen 1 supports bandwidth of 2.5 GT/s per lane per direction.
  • PCIe Gen2 -- Released in January 2007. PCIe Gen 2 supports bandwidth of 5 GT/s per lane per direction.
  • PCIe Gen3 -- Released in November 2010. PCIe Gen 3 supports bandwidth of 8 GT/s per lane per direction.
  • PCIe Gen4 -- Released in November 2011. PCIe Gen 4 supports bandwidth of 16 GT/s per lane per direction.
  • PCIe Gen5 -- Released in June 2017. PCIe Gen 5 supports bandwidth of 32 GT/s per lane per direction.

References

PCIe (Wikipedia)

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mmap, axi and multiple reads from pcie

I am trying to optimize the reading of data via pcie via mmap. We have some tools that allow for reading/writing one word from the PCIe communication at the time, but I would like to get/write as many words as require in one request. My project uses…
r0b0t1
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How to calculate size of MMIO-mapped region from BAR address in PCIe

I've been diving deeper into how PCIe works in general, and I'm stuck at where many books and websites talk about PCIe configuration space. What I have learned so far is that for each of the assigned device with its BDF (bus-device-function bits),…
WannabeArchitect
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Interrupt Handler Stops Working After Kernel Module Reload (Xilinx FPGA / PCIe)

I am currently working on a PCI driver for the Xilinx Kintex 7 board using the Xilinx PCI IP core (AXI Memory Mapped to PCIe). One problem is, that the interrupt handler stops working when I reload the kernel module. In more detail: Fresh boot of…
Nico
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how to flush page data in python using mmap

I am trying to map a region of fpga memory to host system, resource0 = os.open("/sys/bus/pci/devices/0000:0b:00.0/resource0", os.O_RDWR | os.O_SYNC) resource_size = os.fstat(resource0).st_size mem = mmap.mmap(resource0, 65536, flags=mmap.MAP_SHARED,…
Shahbaaz Lokhandwala
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PCI Express AER Driver issues on Linux

I'm debugging a PCIe hardware issue on Linux and I want to enable PCIe AER driver on linux to catch any AER errors reported by my hardware device. I'm following this wiki: https://www.kernel.org/doc/Documentation/PCI/pcieaer-howto.txt My syslog…
h1990
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Single DLL for multiple devices using the same driver

I try to design a third-party DLL between user application and driver, which will be able to manage communication with multiple devices (of the same model) connected via PCIe to the same PC. A single DLL will be placed in known folder, e.g.…
irchris102
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How can AXI4 support PCIE Producer/Consumer ordering model?

PCIE uses Producer/Consumer ordering model, but AXI4 uses a different ordering model. AXI4's read and write channels are independent. For instance, a system like this, CPU <-> PCIE Controller <-> PCIE AXI Bridge <-> AXI4 with DEC and DDR slaves (DEC…
Zhibo Shen
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Access ECAM on QEMU AArch64 virt device

I am trying to implement bare metal PCIE device discovery on QEMU AArch64 virt device. I know, that ECAM area is mapped to 0x3f000000 memory address, and I expect to see there this table. But when I perform a reading of 4 bytes (MCFG signature) from…
Ilja Kartašov
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PCIE 64 Byte single burst Transaction

I want to do a 64-byte transaction on PCIe. I am using Intel i7 9th gen CPU. I was able to do 64-byte write transaction to PCIe device memory by making it WC region and wrote data like this: _mm256_store_si256(pcie_memory_address, ymm0);…
Rahul K V
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qemu from xml to native assign PCI device

I'm stuck between two worlds here. I have part of a VM in virsh/XML and part in qemu native commands and I'm trying to unify them so my last bit is to transform this XML part into qemu native: …
Romeo Mihalcea
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NO CPU interactions in initiating DMA and RDMA operations

I'm trying to build/use a PCIe device using DMA/RDMA, and there're some questions: (1) is it possible to initiate a DMA operation from the device side without interactions with the CPU driver I know in most cases, the CPU driver programs the DMA…
장하민
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PCI error handler in kernel driver never called, even when device is turned off

I'm writing a linux kernel device driver for a custom PCIe device. An user space application is mmapped to this device and frequently accessing its memory (read and write). The PCIe device is driven by an external power supply which may be turned…
ApiTiger
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PCIe latency card to cpu

I'm writing a linux app that talks from user space "directly" to a PCIe card, via DMA, without interrupts and kernel. My aim is to minimize the data travel time between the card and my app. Currently I'm getting latencies of about 800ns, while I was…
BitWhistler
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What is the common topology of GPU within clusters?

I am a novice in the field of high performance computing and I am learning the Allreduce operation for GPU cards. I find the efficient collective operation called ring-Allreduce which requires the physical topology of GPU cards to be the tree…
Sean
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PCIe UIO multi-DWORD access issues

I have an Intel FPGA PCIe endpoint. It shows up correctly in lspci and all of the lspci -vv information looks correct (memory map, IRQ, BAR0 size all look OK). I want to stream some data over BAR0 and read/write status registers inside of my IP. My…
tedx
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