2
    comp_A1: comp_A port map    (   CLK     =>  CLK,
                                    RESET_N =>  RESET_N,
                                    DATA_IN =>  DATA(to_integer(unsigned(count))),
                                    VLD_IN  =>  VLD_IN,
                                    DATA_OUT=>  DATA_OUT,
                                    VLD_OUT =>  VLD_OUT,
                                    BUSY_OUT=>  BUSY_OUT
                                );

In the above snippet I am trying to pass 'DATA' serially to the 'DATA_IN' pin of component comp_A1 within a testbench. 'DATA' and 'count' are both std_logic_vectors. All other signals are std_logic. 'DATA' is a constant vector of size 64 bits and 'count' is a vector being incremented at every rising edge(CLK).

During compilation Model Sim shows me the following errors only,

  1. (vcom-1450) Actual (indexed name) for formal "DATA_IN" is not a static signal name.
  2. VHDL Compiler exiting.

Is the error to do with 'count' being dynamic? What would be a workaround to do this?

rkshthrmsh
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1 Answers1

4

Just move the multiplexer created with the line DATA(to_integer(unsigned(count))) to a separate statement using an intermediate signal, for example:

selected_data <= DATA(to_integer(unsigned(count)));

...

DATA_IN => selected_data
scary_jeff
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  • Works! Another question is-- is there now way to pass a dynamically indexed value in a port map in VHDL? I am pretty sure this can be done in Verilog. – rkshthrmsh Feb 24 '16 at 10:45
  • Is your suggestion the only method? Because it has the overhead of declaring an extra signal. – rkshthrmsh Feb 24 '16 at 10:53
  • I don't understand your 'another question'. Perhaps you could edit your original question with an extra section for this new part. – scary_jeff Feb 24 '16 at 11:08
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    What overhead? It's just good design to use a signal to make the functionality explicit, rather than obfuscate the meaning by burying it in the port map. –  Feb 24 '16 at 11:33
  • I haven't tried it, but I think your original code would work were you using VHDL 2008, because in VHDL 2008 expressions are allowed in port maps (whereas in VHDL 2002, the actual - RHS - of a port map needs to be a name). – Matthew Taylor Feb 24 '16 at 11:46
  • @BrianDrummond I disagree that it's bad design choice to assign pieces of signals on the port map. When you have a set of signals/ports that your working group is familiar with, it can make the code more readable if you reduce the amount of overhead. You need to balance things, I personally hate going round and round the whole code just to follow a signal name changes. Scattering a signal's functionality around the code like this can be just as bad. – suoto Feb 25 '16 at 17:45
  • @suoto : the case here isn't a slice extraction or a type conversion but dynamic code (a different bit of `DATA` every time `count` changes) : now that's obscure! I completely agree with you that extracting (static!) slices or type converting from familiar names improves readability. –  Feb 25 '16 at 20:23
  • @BrianDrummond Ops, my bad. You are right, that's not something I would feel comfortable doing. – suoto Feb 25 '16 at 20:36
  • @suoto : just goes to show how easy it is to confuse people with obscure code :-) –  Feb 25 '16 at 20:41