how to use the force command with a type unsigned(n downto 0) in modelsim when simulating a VHDL file?

Asked May 05 '21 at 20:46

Active May 05 '21 at 20:46

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When initializing inputs for a test, as I understand, you have to use the force command. For example to create a clock cycle, counting that the entity I'm simulating has an input named clock, which is of type std_logic, I would usually write

force clock 0 0, 1 1 -repeat 2

in thee terminal of modelsim how can I do something similar but with the type unsigned(8 downto 0) for example?

asked May 05 '21 at 20:46

motelepf

why not simply create a testbench and drive the clock from there instead? – Tricky May 05 '21 at 20:55
@Tricky I'm quite new to VHDL, so this is pretty much the only "quick" way I've learned to test separate files. – motelepf May 05 '21 at 21:03

how to use the force command with a type unsigned(n downto 0) in modelsim when simulating a VHDL file?

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