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Questions tagged [micro-architecture]

107 questions
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Based Indexed Addressing Mode Memory Sum

I have a instruction: ADD [BX][SI] + 5FFDH, EABFH and I want to know how it operates exactly on 8086 microprocessors. I've realized that this instruction ADD [BX][SI] + 5FFDH, EABFH, works in this manner: 2 bytes of data arrive from data bus and go…
user3866081
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Can you simulate a ransomware on gem5?

I am looking to simulate ransomware on gem5 to basically perform microarchitectural analysis. I want to simulate an environment where ransomware looks for files on a victim's computer and then encrypts them. I would also like to simulate…
Preet Derasari
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What's the microarchitecture used in the MIPS I.S.A?

I believed the microarchitecture used in a MIPS microprocessor, is the pipeline one, but I might be wrong? Thanks in advance for your answers!
Penguineer
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How to figure out disabled cores in a CPU?

I need to find out which cores are disabled on a CPU. How can I do this in C/C++ way? I know that reading CAPID6 register is one of the ways, but I am not sure about how to get it done. Is there any system calls or tricks that I need to be aware…
avernus
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How does write-invalidate policy work with set-associative caches?

I was going through Cache Write Policies paper by Norman P. Jouppi and I understand why write-invalidate (defined on page 193) works well with direct mapped caches which is because of the ability to write the data which checking the tag and if found…
Nebula
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8085; Why RET doesn't require a 6 T-states Fetch cycle like CALL?

The CALL instruction, requires 5 machine cycles, namely, OPCODE-FETCH, MEMORY READ, MEMORY READ, MEMORY WRITE, MEMORY WRITE. The OPCODE-FETCH cycle of CALL has 6 T-states to take care of the decrements of the Stack Pointer. RET instruction…
Aravindh Vasu
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MIPS wired logic DPU

I am a student and i have an exercise on MIPS and i need some guidance! Below is the exercise: Consider the Data Processing Unit of MIPS architecture wired logic for a command cycle for single and multiple machine cycles. Describe the full flow of…
Δημητρης Ρόκκος
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Why some instructions take less cycles while all go through the same pipeline stages?

In a processor's instruction manual, some instructions are mentioned to take less number of cycles while others take more. The processor has a n-stage pipeline and all instructions go via the same pipeline then shouldn't they all take n-cycles as…
sanjivgupta
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How can the processor discern a far return from a near return?

Reading Intel's big manual, I see that if you want to return from a far call, that is, a call to a procedure in another code segment, you simply issue a return instruction (possibly with an immediate argument that moves the stack pointer up n bytes…
user5209336
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why an explicit single-cycle datapath is not needed?

Why does the PC not need an explicit write signal in a single-cycle datapath? Why is an explicit write control signal needed in a multicycle datapath? Thank you
user3142443
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late lhr / ghr update in long pipeline

I'm wondering if it is a viable scenario in long pipelines, when younger branch instruction is already processed by branch prediction mechanism, but corresponding lhr (or ghr, depending on implementation) still hasn't been updated with actual result…
Bob
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What is the minimal number of dependency chains to maximize the execution throughput?

Given a chain of instructions linked by true dependencies and repeated periodically (i.e. a loop), for example (a->b->c)->(a->b->c)->... Assuming that it can be split into several shorter and independent sub-dependency chains to benefit from…
DMH
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Can non load store instructions go past memory fences? (x86_64)

Is that only load/store operations are not reordered around memory fences? My understanding is that serializing instructions such as CPUID prevent any instruction (including load/store operations) being reordered around it. Is it the same for memory…
chamibuddhika
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Verilator does not seem to recognize casez statement, any idea of how to solve this?

I'm trying to code a riscv decoder in system verilog, here's the code : case(opcode) 7'b0110011: assign r_type = 1'b1; 7'b0010011: assign i_type = 1'b1; 7'b0000011: assign i_type = 1'b1; 7'b0100011: assign…
Lovis XII
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How does the Program read 32 bit from the memory in a single clock cycle?

So, I have this assignment where I need to design a RISC-32-bit 5 stage pipeline. I must support at least 32 (32-bit) instructions and 32 (32-bit) data values. The memory should be read in 1 clock cycle. Now, for this, I have used a word addressable…
Vedanta Mohapatra
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