Why does the PC not need an explicit write signal in a single-cycle datapath? Why is an explicit write control signal needed in a multicycle datapath?
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Peter Cordes
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1My guess is that in a MC data path each component, including the PC, must be buffered in order to be updated in the right cycle. Hence the write signal. – Margaret Bloom Nov 28 '16 at 10:45
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Since you didn't give any reference to the data path, I am going to assume Patterson and Hennessy's single cycle and multicycle data paths. If you check the single cycle control signals flowing in this question, the Jump and Branch control signals feed the muxes at the end of the pipeline, which determines the input to the PC.In the absence of these control inputs, the PC will be incremented by its default value, 4. Therefore there is no need of an explict write control for PC in a single cycle data path.
This is not the same for a multi cycle data path as so many operations are happening in parallel, therefore explicit control is necessary to determine which path to pick in determining the address of the next instruction.
