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Questions tagged [micro-architecture]

107 questions
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Instruction cache loading and eviction rules

I'm trying to get an idea of how the instruction cache works. How many extra cachelines gets prefetched when a block of code is being executed? Does it take into account branch prediction? If a block of code contains a function call, is the…
Remus
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What granularity does memory channel interleaving occur when enabled in BIOS?

Memory channel interleaving is a method of setting a physical address area which can be enabled in BIOS, so that all memory channels are alternately used to achieve best bandwidth and latency. I want to know at what granularity memory channel…
Frontier_Setter
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How instructions are fetched into modern CPUs(2023)?

I am learning rocketchip these days, and I have noticed the IFU(Instruction Fetch Unit) fetches instructions from ibuf instead of main memory. But I have not seen any codes about how instructions are fetched from main memory to ibuf. I consulted…
Teng Wu
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Is port blocked when data is fetching from cache or memory in CPU microarchitecture?

There are two identical memory read ports (port 2 and 3) and one write port (port 4) of Intel Skylake cores. Assuming there are two load instructions issued to port 2 and port 3 parallelly: When both data can be fetched from L1 cache ( about…
oleotiger
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Does storing false bool values cost less electrical energy?

Going to sleep tonight I have been wondering: if bool, in C++ for example, is set to false that mean, that all of it’s (8 or 16)bits are set 0(seems to be). Zero bit, as far as I know, means no current flowing in some transistor, so, hence false…
Ngdgvcb
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Do memory instructions pass through the load-store queue and issue queue in the microarchitecture

What is the difference between the issue queue and lsq queue for memory instructions? Do memory instructions pass through both queues, or do they only pass through the lsq queue. If they pass through both queues what is their order?
ai006
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Does L1 cache accept new incoming requests while its Line Fill Buffers (LFBs) are fully exhausted?

I wonder if L1 cache still receives new requests that hit L1D, making forward progress for the pipeline when Line Fill Buffers (LFBs or MSHRs) get full? Or could anybody help me write a microbenchmark that can tell me if it does or not? I know how…
ykwon
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How can I add a decorator pattern to a chain of responsibility?

I created the following UML. It's basically a currency converter. As it is now, it is a Chain of Responsibility. But now I want to add a Decorator pattern. So, for example, add a fixed processing amount. How can I insert a Decorator pattern…
BogoBogo
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icc: increase in runtime in one part while changing a different and independent part of code

I have a strange problem and maybe one of you has an idea what is going on there. The code I'm working on is a longish and complex simulation code. I have a function matrixSetup which is called at the beginning and where I measure the runtime of.…
Oichlober
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Can programs use (significantly) less memory when compiled for different processors?

I have a C++ program I'm compiling for AMD64. Of course, different processors, despite being AMD64, support different features and instructions because they implement different microarchitectures. An easy way to optimise the program for one's own…
mbarbar
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How is coherence implemented in multi-level caches?

I have understood how the cache coherence FSM works for single private L1 cache and a common LLC/memory. But couldn't find good resources where they discuss about cache coherence when there are 2 private caches - L1 and L2 and a common memory. I…
Nebula
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How to look up what form of an instruction is used, by opcode or disassembly?

Sites like https://uops.info/ and Agner Fog's instruction tables, and even Intel's own manuals, list various forms of the same instruction. For example add m, r (in Agner's tables) or add (m64, r64) on uops.info, or ADD r/m64, r64 in Intel's manual…
Eric Stotch
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Could this multicycle MIPS avoid a mux for the new PC value?

I came across this multicycle MIPS processor microarchitecture. My query is, is the multiplexer (selected by PCSrc) which selects PC value really needed? What is the harm in only sending the clocked PC value to PC'. Considering the instruction is…
Chirag Agrawal
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uops for integer DIV instruction

I was looking the Agner Fog's instruction tables here, specifically I was looking at the sandy bridge case, and there is one thing that has caught my attention. If you look DIV instructions you can see that, for example, r64 DIV instruction can be…
isma
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Pipeline Diagram of IO2I Microarchitecture

Is my pipeline correct for the given sequence of instructions? If it is not, can you shine some light on where I went wrong? EDIT: I forgot to add the issue stage of the mul instruction. MUL R6, R7, R8 ADD R9, R10, R11 ADD R11, R12, R13 ADD R13,…
Corith
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