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Questions tagged [micro-architecture]

107 questions
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x86 dissasembler that shows instruction extensions needed

I need to check the minimal set of x86 instruction extensions needed to execute a given binary object (not a general binary, but the output of gcc -c somefile.s). Doing it by hand is time consuming and error prone. I am looking for an automated…
iatk8i
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How do branches work in code that comes from the microcode sequencer?

My high-level understanding of the Intel front-end is as follows. It is mostly vague and could be wrong. A branch predictor determines the next address to fetch instructions from. Sometimes a signal comes from the backend "branch foo was predicted…
Brennan Vincent
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What's 'new' in a 'new' processor when viewed from programmer's point

I have recently been interested in understanding low level computing. I understand that today's widely used computers follow x86/x86-64 architecture. To my understanding, architecture, more specifically Instruction Set Architecture (ISA) is the set…
Vaibhav Maheshwari
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shifting registers to right in the mic-1 without fetches

this is the first time I post a question here so feel free to give me some feedback were something not described in the proper manner. To the actual question: I was wondering if there was a way to shift a word in one of the registers TO THE RIGHT by…
Tripparsugo
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Measuring TLB Miss Penalty for intel processos with PCM tool

I'm trying to measure the TLB(Translation Look Aside Buffer) miss penalty on X86-64. Specifically miss penalty of the second level unified TLB which is the cost of TLB walk. I have been looking into Intel pcm tool but haven't been able to figure out…
parisa
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Where does the L1 data cache missing come from in blocked matrix mul on arm?

I try to optimize integer matrix multiple by dividing them into smaller matrix block to get a better cache hit rate on raspberry pi 3b+ (it is a Cortex-A53 core, with cache line 64 bytes, 4-way associativities. it is 32K byte). Here is the…
zwy
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How long does the retire unit take in the reservation station to retire an instruction?

I went hunting in the Intel Optimization manual, and for Skylake, I could not find how long it takes to retire an instruction after it has left its execution port assuming no delays. Can someone please provide this information or give me a…
ReverseFlowControl
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small branch prediction exercise (not homework)

This is NOT homework. I was reading this site which, IMO, has pretty good introduction into branch prediction, and decided to try solving a problem following the lecture: consider the following code [no branch delay slots]: add $2, $0, $0 addi…
Bob
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What does the wait() function do?

Hi I started learning Java and am currently trying to learn C++. I have this piece of code and cannot workout what it does. I am assuming it makes the program wait for a certain period of time before it starts. But some further explanation would…
user5647516
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Forwarding an image upload request to another server

I'm trying to build a NodeJS REST API project based on the so called "micro architecture" (basically multiple smaller NodeJS projects that can run totally independent, but at the same time work together). Currently users are able to upload images…
Jay Y
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How to load a microapp dynamically in angular 16

I am trying a load microapps on the right side of my screen on click of the tabs in the menu bar in angular 16. I came across a dynamic component loading concept, was trying to experiment with it and am getting an issue with the same. Below is the…
Akram
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Is machine code and assembly code part of the architecture?

Is assembly code and machine code specified by the architecture? I know that how you implement the architecutre is uo to you(it is up the microarchitecture can implement the architecture). But I don't understand if the assembly or machine code is…
user394334
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Memory loads experience different latency on the same core

I am trying to implement a cache based covert channel in C but noticed something weird. The physical address between the sender and the receiver is shared by using the mmap() call that maps to the same file with the MAP_SHARED option. Below is the…
Sathvik Swaminathan
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vtune memory-access report showing incorrect output

I am running vtune -collect memory-access ./main and I receive the output below. The main binary does a lot of random memory accesses on a large virtual and physical memory range. Memory Bound LLC Miss: 0.0% of Clockticks DRAM Bandwidth…
Jack Humphries
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how do conditional branches and instructions which update conditional flags operate in an out of order arm architecture?

I have the following sequence of instructions: Address instr Operands 4357128L cmp {"x1", "#16"} 4357132L bne {"4356768"} 4357136L add {"w19", "w6","#16"} 4357140L add {"x0", "x0", "#16"} 4357144L bhi {"4387895"} after cmp…
Tom Jose
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