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I have a instruction: ADD [BX][SI] + 5FFDH, EABFH and I want to know how it operates exactly on 8086 microprocessors. I've realized that this instruction ADD [BX][SI] + 5FFDH, EABFH, works in this manner:

  1. 2 bytes of data arrive from data bus and go to instruction queue.
  2. Data that available on instruction queue goes to instruction decoder.
  3. Another 2 bytes of data arrive from data bus and go to instruction queue.
  4. BX and SI values go to ALU and calculates BX + SI
  5. Another 2 bytes of data arrive from data bus and go to instruction queue.
  6. BX + SI goes to ALU's input.
  7. 5FFDH pop from instruction queue and goes to ALU's input.
  8. ALU calculates BX + SI + 5FFDH.
  9. BX + SI + 5FFDH goes to memory through address bus.
  10. BX + SI + 5FFDH's value comes from memory and goes to ALU's input.
  11. EABFH pop from instruction queue and goes to ALU's input.
  12. [BX + SI + 5FFDH] + EABFH calculates by ALU.
  13. ???????????

So my question is on step 13. How microprocessor knows that memory address (BX + SI + 5FFDH) to send [BX + SI + 5FFDH] + EABFH's value to memory according to empty instruction queue and we cannot calculate BX + SI + 5FFDH again.

Peter Cordes
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user3866081
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  • You forgot the DS segment-base address as part of the calculation. Also, 8086 almost certainly has some internal tmp storage that its microcode can use to store the result of address calculation for RMW instructions. It's not exactly pipelined the way MIPS was! (But IIRC, you're right that it used the ALU for address calculation, not having a dedicated AGU). In theory nothing's stopping it from re-calculating the address, but keeping around the address is much more sensible than keeping around the original instruction bytes. – Peter Cordes Jun 07 '21 at 09:45
  • @PeterCordes Thank you for answering, You're right I've forgot about DS segment. I have another question: Where is internal tmp storage? Is it in ALU? – user3866081 Jun 07 '21 at 09:52
  • No, I don't expect it's in the ALU itself, that wouldn't make sense to have the ALU also be a register file. Updated my answer with a more specific guess at where it might be. – Peter Cordes Jun 07 '21 at 09:57
  • And BTW, if you have further Q&As about original-8086 microarchitecture details (or systems using it), you're most likely to get detailed answers on https://retrocomputing.stackexchange.com/. I just hand-waved some guesswork, but I wouldn't be surprised if some regulars there actually know, and would also be able to confirm or correct your guess that instruction execution starts after fetching the opcode and modrm, before the full instruction is even fully fetched. It's not how modern x86 works, but it sounds plausible for scalar micro-coded 8086. – Peter Cordes Jun 07 '21 at 10:19

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8086 almost certainly has some internal tmp storage that its microcode can use to store the result of address calculation for RMW instructions. It's not exactly pipelined the way MIPS was! (But IIRC, you're right that it used the ALU for address calculation, not having a dedicated AGU).

In theory nothing's stopping it from re-calculating the address, but keeping around the address is much more sensible than keeping around the original instruction bytes.

Keep in mind that 8086 was driven by microcode, kind of like an interpreter that implements x86 using its internal resources. So the temporary storage would just be like a register other than the architectural registers that are visible to 8086 instructions.

In this case, one might imagine that there was some circuitry for data accesses to send addresses to the bus interface unit, competing with code-fetch. It's totally plausible that some address register in the data side of things could simply hold the last data address that was used, even if code-fetch reads from a different address in between.

If you're really curious about full details, see if http://www.righto.com/2020/08/reverse-engineering-8086s.html (Ken Shirriff's blog) has gotten to how microcode handles memory-destination ALU instructions.

BTW, you forgot the DS segment-base address as part of the address calculation.

Peter Cordes
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  • Do you mean the address will be hold in microcode's storage? Where is the internal tmp storage exactly? – user3866081 Jun 07 '21 at 11:23
  • @user3866081: More or less yes. I don't know or care about the exact details. If you want more than that, google for more details about exactly how 8086 microcode worked, and what internal state it had available to use, separate from the architectural state. If you don't find anything, you could ask on https://retrocomputing.stackexchange.com/ – Peter Cordes Jun 07 '21 at 11:25