Verilog program not getting desired output on 4x1 mux

Question

I have this program I am suppose to make for this diagram 4x2 decoder diagram: I keep trying to change the initial values of the output array from 0 to 1 and 1 to 0 by just negating them but I still never get the desired result.

4x1 mux

module DecoderMod(s, o); // module definition
   input [1:0] s;
   output [0:3] o;

   assign o[0] = s[1]; //
   assign o[1] = s[1];// 
   assign o[2] = s[0];// 
   assign o[3] = s[0];// 

endmodule

module MuxMod(s, d, o);
   input [1:0] s;
   input [0:3] d;
   output o;

   wire [0:3] s_decoded, and_out;

   DecoderMod my_decoder(s, s_decoded); // create instance

   and(and_out[0], d[0], s_decoded[0]);
   and(and_out[1], d[1], s_decoded[1]);
   and(and_out[2], d[2], s_decoded[2]);
   and(and_out[3], d[3], s_decoded[3]);
   or(o, and_out[0], and_out[1], and_out[2], and_out[3]);
endmodule

module TestMod;
   reg [1:0] s;
   reg [0:3] d;
   wire o;

   MuxMod my_mux(s, d, o);

   initial begin
      $display("Time  s   d     o");
      $display("-----------------");
      $monitor("%04d  %b  %b  %b", $time, s, d, o);
   end

   initial begin
      s[1] = 0; s[0] = 0; d = 4'b0000; #1;
      s[1] = 0; s[0] = 0; d = 4'b0001; #1;
      s[1] = 0; s[0] = 0; d = 4'b0010; #1;
      s[1] = 0; s[0] = 0; d = 4'b0011; #1;
      s[1] = 0; s[0] = 0; d = 4'b0100; #1;
      s[1] = 0; s[0] = 0; d = 4'b0101; #1;
      s[1] = 0; s[0] = 0; d = 4'b0110; #1;
      s[1] = 0; s[0] = 0; d = 4'b0111; #1;
      s[1] = 0; s[0] = 0; d = 4'b1000; #1;
      s[1] = 0; s[0] = 0; d = 4'b1001; #1;
      s[1] = 0; s[0] = 0; d = 4'b1010; #1;
      s[1] = 0; s[0] = 0; d = 4'b1011; #1;
      s[1] = 0; s[0] = 0; d = 4'b1100; #1;
      s[1] = 0; s[0] = 0; d = 4'b1101; #1;
      s[1] = 0; s[0] = 0; d = 4'b1110; #1;
      s[1] = 0; s[0] = 0; d = 4'b1111; #1;
      s[1] = 0; s[0] = 1; d = 4'b0000; #1;
      s[1] = 0; s[0] = 1; d = 4'b0001; #1;
      s[1] = 0; s[0] = 1; d = 4'b0010; #1;
      s[1] = 0; s[0] = 1; d = 4'b0011; #1;
      s[1] = 0; s[0] = 1; d = 4'b0100; #1;
      s[1] = 0; s[0] = 1; d = 4'b0101; #1;
      s[1] = 0; s[0] = 1; d = 4'b0110; #1;
      s[1] = 0; s[0] = 1; d = 4'b0111; #1;
      s[1] = 0; s[0] = 1; d = 4'b1000; #1;
      s[1] = 0; s[0] = 1; d = 4'b1001; #1;
      s[1] = 0; s[0] = 1; d = 4'b1010; #1;
      s[1] = 0; s[0] = 1; d = 4'b1011; #1;
      s[1] = 0; s[0] = 1; d = 4'b1100; #1;
      s[1] = 0; s[0] = 1; d = 4'b1101; #1;
      s[1] = 0; s[0] = 1; d = 4'b1110; #1;
      s[1] = 0; s[0] = 1; d = 4'b1111; #1;
      s[1] = 1; s[0] = 0; d = 4'b0000; #1;
      s[1] = 1; s[0] = 0; d = 4'b0001; #1;
      s[1] = 1; s[0] = 0; d = 4'b0010; #1;
      s[1] = 1; s[0] = 0; d = 4'b0011; #1;
      s[1] = 1; s[0] = 0; d = 4'b0100; #1;
      s[1] = 1; s[0] = 0; d = 4'b0101; #1;
      s[1] = 1; s[0] = 0; d = 4'b0110; #1;
      s[1] = 1; s[0] = 0; d = 4'b0111; #1;
      s[1] = 1; s[0] = 0; d = 4'b1000; #1;
      s[1] = 1; s[0] = 0; d = 4'b1001; #1;
      s[1] = 1; s[0] = 0; d = 4'b1010; #1;
      s[1] = 1; s[0] = 0; d = 4'b1011; #1;
      s[1] = 1; s[0] = 0; d = 4'b1100; #1;
      s[1] = 1; s[0] = 0; d = 4'b1101; #1;
      s[1] = 1; s[0] = 0; d = 4'b1110; #1;
      s[1] = 1; s[0] = 0; d = 4'b1111; #1;
      s[1] = 1; s[0] = 1; d = 4'b0000; #1;
      s[1] = 1; s[0] = 1; d = 4'b0001; #1;
      s[1] = 1; s[0] = 1; d = 4'b0010; #1;
      s[1] = 1; s[0] = 1; d = 4'b0011; #1;
      s[1] = 1; s[0] = 1; d = 4'b0100; #1;
      s[1] = 1; s[0] = 1; d = 4'b0101; #1;
      s[1] = 1; s[0] = 1; d = 4'b0110; #1;
      s[1] = 1; s[0] = 1; d = 4'b0111; #1;
      s[1] = 1; s[0] = 1; d = 4'b1000; #1;
      s[1] = 1; s[0] = 1; d = 4'b1001; #1;
      s[1] = 1; s[0] = 1; d = 4'b1010; #1;
      s[1] = 1; s[0] = 1; d = 4'b1011; #1;
      s[1] = 1; s[0] = 1; d = 4'b1100; #1;
      s[1] = 1; s[0] = 1; d = 4'b1101; #1;
      s[1] = 1; s[0] = 1; d = 4'b1110; #1;
      s[1] = 1; s[0] = 1; d = 4'b1111;
    end
endmodule

My runtime output is suppose to be the same as this: http://athena.ecs.csus.edu/~changw/137/prg/2/demo/mux4x1-output.txt (or the code here)

Time s  d       o
-----------------------------
0   00  0000    0
1   00  0001    0
2   00  0010    0
3   00  0011    0
4   00  0100    0
5   00  0101    0
6   00  0110    0
7   00  0111    0
8   00  1000    1
9   00  1001    1
10  00  1010    1
11  00  1011    1
12  00  1100    1
13  00  1101    1
14  00  1110    1
15  00  1111    1
16  01  0000    0
17  01  0001    0
18  01  0010    0
19  01  0011    0
20  01  0100    1
21  01  0101    1
22  01  0110    1
23  01  0111    1
24  01  1000    0
25  01  1001    0
26  01  1010    0
27  01  1011    0
28  01  1100    1
29  01  1101    1
30  01  1110    1
31  01  1111    1
32  10  0000    0
33  10  0001    0
34  10  0010    1
35  10  0011    1
36  10  0100    0
37  10  0101    0
38  10  0110    1
39  10  0111    1
40  10  1000    0
41  10  1001    0
42  10  1010    1
43  10  1011    1
44  10  1100    0
45  10  1101    0
46  10  1110    1
47  10  1111    1
48  11  0000    0
49  11  0001    1
50  11  0010    0
51  11  0011    1
52  11  0100    0
53  11  0101    1
54  11  0110    0
55  11  0111    1
56  11  1000    0
57  11  1001    1
58  11  1010    0
59  11  1011    1
60  11  1100    0
61  11  1101    1
62  11  1110    0
63  11  1111    1

but I get this... What am I doing wrong?

Time  s   d     o
-----------------
0000  00  0000  0
0001  00  0001  0
0002  00  0010  0
0003  00  0011  0
0004  00  0100  0
0005  00  0101  0
0006  00  0110  0
0007  00  0111  0
0008  00  1000  0
0009  00  1001  0
0010  00  1010  0
0011  00  1011  0
0012  00  1100  0
0013  00  1101  0
0014  00  1110  0
0015  00  1111  0
0016  01  0000  0
0017  01  0001  1
0018  01  0010  1
0019  01  0011  1
0020  01  0100  0
0021  01  0101  1
0022  01  0110  1
0023  01  0111  1
0024  01  1000  0
0025  01  1001  1
0026  01  1010  1
0027  01  1011  1
0028  01  1100  0
0029  01  1101  1
0030  01  1110  1
0031  01  1111  1
0032  10  0000  0
0033  10  0001  0
0034  10  0010  0
0035  10  0011  0
0036  10  0100  1
0037  10  0101  1
0038  10  0110  1
0039  10  0111  1
0040  10  1000  1
0041  10  1001  1
0042  10  1010  1
0043  10  1011  1
0044  10  1100  1
0045  10  1101  1
0046  10  1110  1
0047  10  1111  1
0048  11  0000  0
0049  11  0001  1
0050  11  0010  1
0051  11  0011  1
0052  11  0100  1
0053  11  0101  1
0054  11  0110  1
0055  11  0111  1
0056  11  1000  1
0057  11  1001  1
0058  11  1010  1
0059  11  1011  1
0060  11  1100  1
0061  11  1101  1
0062  11  1110  1
0063  11  1111  1

score 1 · Accepted Answer · answered Feb 25 '18 at 10:46

1

I assume that " DecoderMod" should be the 2x4 decoder you asked about a few hours back. What you have there is not a decoder, just two wires pairwise connected to four outputs.

answered Feb 25 '18 at 10:46

Oldfart

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Sean Houlihane · Answer 2 · 2018-02-26T08:11:35.063

Your coding style is obfuscating the logic which you are trying to write. You have split the design unnecessarily, to generate a {1,1,0,0} expansion, then your write instantiated gates when there are simpler ways.

You've written

out = ((d[0] | d[1]) & s[1]) | ((d[2] | d[3]) & s[0]);

This one line may not be too easy to read either (I'd normally break each sum-of-product term onto a separate line, but the bracketing here messes that up) but at least all the code is in one place, not spread over 30 lines or so...

It occurs that another reason why the original structure might have seemed preferable would be to minimise logic and avoid repetition. Actually, modern (i.e. since maybe 2005-2010) compilers have got pretty smart about optimising logic, particularly to map onto the various odd standard cells. Standard cells typically have several inputs (of and/or/invert permutations) and sometimes both normal and invert outputs. One of the ways of preventing this optimisation is to place specific logic in a module and prevent flattening/optimisation across that boundary.

Wow so that single line is basically my whole code! I did it the way I showed because the modules were already set up that way and I just had to write in the code. Your way is so much simpler! — T.H., Feb 25 '18 at 22:00
It's not so bad when you're working with small designs, and easier to teach with a hierarchical structure, but obviously doesn't scale for even trivial real designs. Where to place the boundaries is a recurring problem - there is no one good answer. — Sean Houlihane, Feb 26 '18 at 08:16

score 0 · Answer 3 · answered Apr 01 '18 at 04:38

Simple Mux using RTL and much easier to read and understand.

Given,

input [1:0] x_in;
output [3:0] x_out_v;

assign x_out_v [0] =  ( ~x_in[1] && ~x_in[0] ); 
assign x_out_v [1] =  ( ~x_in[1] &&  x_in[0] ); 
assign x_out_v [2] =  ( x_in[1] &&  ~x_in[0] ); 
assign x_out_v [3] =  ( x_in[1] &&   x_in[0] );

Verilog program not getting desired output on 4x1 mux

3 Answers3