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I want to view a list of all modules/sub-modules/instances in verilog/system-verilog compilation; is that possible? I know i can do a %m in $display and it will show the hierarchy of that particular instance. I want to get a similar list but for all the modules and instance which I can use for later post-processing. Would this information be EDA tool dependent?

Thanks in advance :)

justrajdeep
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Most simulation tools provide commands to this either with some kind of report, or creating a simple Tcl script.

You can also do this using SystemVerilog's VPI or DPI/VPI combination so it won't be tool dependent. See my 2016 DVCon paper: Introspection into SystemVerilog without Turning It Inside Out

dave_59
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