Verilog module cannot calculate a&b and a|b

Question

I am creating the verilog module that calculate either one of a+b, a-b, a & b or a | b.

The problem is that it does calculate for a+b and a-b. but it cannot calculate a & b and a | b and return nothing.

input [31:0] a, b;
input [2:0] op;
output [31:0] z;
output ex; 
wire[31:0]a0,a1,a2,a3;

assign a0 = a & b;
assign a1 = a | b;
assign a2 = a + b;
assign a3 = a - b;

assign z=a0;
//assign z=a1;
//assign z=a2;
//assign z=a3;

endmodule

the module basically calculate a+b, a-b, a&b, and a|b and assign its calculated value to z.

And it does successfully calculate for a+b and a-b and put calculated value to z.

But for a&b and a|b, it doesn't assign anything to z.

How can I solve this?

Thank you very much if you can help me.

I [put a delay after setting input](http://codepad.org/xCv3b5N8) and it seems working well. Please post a [Minimal, Complete, and Verifiable example](http://stackoverflow.com/help/mcve). — MikeCAT, Mar 20 '16 at 06:04

Matthew Taylor · Answer 1 · 2016-03-20T09:22:46.500

I'm sure it does assign something to z. The problem is that you are trying to assign too much to z.

Each assign statement represents some hardware, which in this case drives the wire z. So, you are driving z 4 times in parallel from 4 separate lumps of hardware. If you like, you have a short circuit. (Remember Verilog is a hardware description language. You are designing hardware here, not writing software. If you assign to a wire from more than one place, you have shorted the outputs of some lumps of hardware together.)

I notice there is an input [2:0] op. This looks like homework to me and I guess you have been asked to design an ALU. An ALU is a lump of hardware (combinational logic in this case) that can perform various operations on it's inputs (its operands), which in this case are a and b. Which operation it performs needs to be selected by some other control input, which in this case is almost certainly supposed to be op.

So, you need some code that tests op and drives z with either a+b, a-b, a&b or a|b. The obvious construct to me for this job is a case statement:

case (op)
  3'b000:
    z =     // some expression, eg a + b, it depends on what op code 000 is supposed to mean
  3'b001:
    z =     // some other expression here

            // etc etc

  default:  // perhaps...
    z =     // ...something to drive z if none of the other branches are used
endcase

A case statement should go inside an always block. As I suspect this is homework, I won't feed you the answer, I'll let you work out how to do that.

Finally, I see that op is 3 bits wide. This suggests that you ALU has more than 4 different operations to carry out. I also see there is an ex output, which presumably needs to do something.

score 0 · Answer 2 · answered Mar 21 '16 at 18:35

There's some confusion here. Your original posted code is fine; z will be assigned as you want. The other answer is incorrect - there are no multiple drivers; they're commented out. The delay suggestion is also incorrect - a delay will make no difference whatever to your logic.

Verilog module cannot calculate a&b and a|b

2 Answers2