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I know that we can use parameters to make generic modules, and to improve readability of code. My question is whether we can have these parameters themselves as a variable. Something like this:

module parameterModule #(parameter p1, ...)(<ports>);
  ...
  ...
endmodule

module changingParameterModule (output [p1_width-1:0] p1);
  ...
  ...
endmodule

Here, I want p1 port of the changingParameterModule to be treated as the parameter p1 for the parameterModule. Is this possible?

I use icarus-verilog and Quartus Prime Lite.

Akilesh Kannan
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1 Answers1

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No this is not possible; parameters are compile time constants. Module port outputs have the potential to change at any time, and their values don't even get computed until after compilation is over.

dave_59
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  • Thanks! I actually want them to change. I'm trying to make a memory unit that doesn't have a fixed size, until I get the user input. – Akilesh Kannan Jul 16 '20 at 08:33