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I am trying to create a 32 bit array with 10 spaces in Verilog. Here is the code:

reg [31:0] internalMemory [0:9];

I then try to assign 32 bit values to different locations inside that register. Here is a code sample:

internalMemory[0] = 32'b00000000001000100001100000100000;
internalMemory[1] = 32'b00000000001000100001100000100001;

When compiling I get the following error:

IR.v:21: syntax error
IR.v:21: error: Invalid module instantiation

That line 21 represents me trying to access internalMemory[1].

Any advice as for why this is happening and how to fix it?

Thanks!

UPDATE 1:

As requested here is there code for the Instruction Register I am trying to implement:

`include "IRTester.v"
module instruction_register(IREnable, programCounter, controlUnit, RS, RT, RD, immediate);

parameter  dataWidth = 32; //input size

input wire IREnable;
input wire  [31:0] programCounter; //instruction to be read
output wire [5:0] controlUnit;
output wire [4:0] RS;
output wire [4:0] RT;
output wire [4:0] RD;
output wire [15:0] immediate;


wire [31:0] temp;
reg [31:0] internalMemory [0:9];

always @ (posedge IREnable)

    internalMemory[0] = 32'b00000000001000100001100000100000;
    internalMemory[1] = 32'b00000000001000100001100000100001;

    assign temp = internalMemory[programCounter];
    assign controlUnit = temp[31:26];
    assign RS = temp[25:21];
    assign RT = temp[20:16];
    assign RD = temp[15:11];
    assign immediate = temp[15:0];

endmodule
Wilo Maldonado
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  • This error is related to some submodule instantiation inside your module, not this assignment. Show us some more code (i.e. lines before 21) to help you solve this issue. – Qiu Apr 15 '15 at 06:20
  • @Qui - I updated the question to include the whole code – Wilo Maldonado Apr 15 '15 at 06:30
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    The `always` block is not properly enclosed. And where is the `IR.v` code? The error is there. – Eugene Sh. Apr 15 '15 at 14:12

3 Answers3

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You have to use begin/end

always @ (posedge IREnable) begin
    internalMemory[0] = 32'b00000000001000100001100000100000;
    internalMemory[1] = 32'b00000000001000100001100000100001;
end
XjR
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    always @ (posedge IREnable)

    internalMemory[0] = 32'b00000000001000100001100000100000;
    internalMemory[1] = 32'b00000000001000100001100000100001;

    assign temp = internalMemory[programCounter];
    assign controlUnit = temp[31:26];
    assign RS = temp[25:21];
    assign RT = temp[20:16];
    assign RD = temp[15:11];
    assign immediate = temp[15:0];

endmodule

in this code, you coded always block without any begin - end. so that, when you execute the code, the line very next to always ( internalMemory[0] = 32'b00000000001000100001100000100000; ) will considered as in always block; as behavioural. that is why the next line shows error, since it is supposed to be in data-flow.

.

Roshan
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You cannot use assign statements inside always block. Get them out.

andi99
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