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I am really confused.

I did verilog programming and compiled and executed in VCS. It is giving correct values at expected clock cycles.

When I run it is ivl32 it is giving slightly different values.

I am confused completely.

Can some one tell me what the issue will be?

sharvil111
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vishnu prasanth
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1 Answers1

2

The major Electronic Design Automation (EDA) tool vendors each have their own SystemVerilog simulator. The tools is also written by different people at different time, more specifically Simulation algorithm. So in general they behaves same ways.

There is called Indeterminacy, and care must be taken to ensure that models or testbenches are written in such a way that, Indeterminacy does not matter.

Indeterminacy: Uncertainty

See from LRM example:

assign b = a;
initial 
begin
  a = 1;
  #1 a = 0;
  $display(b);
end

Because the execution of initial is interleaved with assign statement, the value of b may b '0' or '1', different simulator give different output.

Questasim:

-- Compiling module chk

Top level modules:
    chk
Reading pref.tcl

# 10.4

# vsim -lib work chk -c -do "run -all; quit -f" -appendlog -l qverilog.log -vopt 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# //  Questa Sim-64
# //  Version 10.4 linux_x86_64 Dec  2 2014
# //
# //  Copyright 1991-2014 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //  THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL
# //  INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM
# //  DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.
# //  FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER
# //  THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.
# //
# Loading work.chk(fast)
# run -all
# ----*---- Value of b is :: 0 ----*----
#  quit -f
# End time: 14:32:20 on May 10,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0

INCISIV:

irun: 12.20-s015: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
Recompiling... reason: file './me.v' is newer than expected.
    expected: Tue May 10 14:31:09 2016
    actual:   Tue May 10 14:33:54 2016
file: me.v
    module worklib.chk:v
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        chk
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.chk:v <0x5f262bc0>
            streams:   1, words:   825
    Loading native compiled code:     .................... Done
    Building instance specific data structures.
    Design hierarchy summary:
                    Instances  Unique
        Modules:            1       1
        Registers:          1       1
        Scalar wires:       1       -
        Initial blocks:     1       1
        Cont. assignments:  0       1
    Writing initial simulation snapshot: worklib.chk:v
Loading snapshot worklib.chk:v .................... Done
ncsim> source /sib/tools/Cadence/Install/INCISIV122/tools/inca/files/ncsimrc
ncsim> run
----*---- Value of b is :: 1 ----*----
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit

If you have racing in your code then this kink of problem may occur.

Prakash Darji
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