VHDL - DE0 - QUARTUS II PLL not showing output in modsim

Question

Hi I am trying to use a phased lock loop for clock generation for a VGA controller. I had no luck and decided to make my own clock which then worked fine. I got the VGA controller working. Going back to PLL's though I still can't get a PLL selected to give me an output. I have made a little test model to simulate it.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY PLL4 IS 
PORT    (
        clk         :   IN std_logic;
        a               :   IN std_logic;
        rst         :   IN  std_logic:='0';
        x               :   OUT std_logic
        );
END ENTITY PLL4;

ARCHITECTURE A1 OF PLL4 IS
COMPONENT PLL_4 IS
PORT(
    clk_in_clk  : in  std_logic; -- clk
    rst_reset   : in  std_logic; -- reset
    clk_out_clk : out std_logic  -- clk
    );
END COMPONENT PLL_4;
SIGNAL clk25    :   std_logic;
BEGIN
CLK_25 : PLL_4 PORT MAP (clk,rst,clk25);
x <= a and clk25;

END ARCHITECTURE A1;

When I simulate this with mod sim I just get the following

I never see the PLL clock output. Can anyone give me some advice on this.

--Update-- After adding the signals from the CLK_25 : PLL I now get the following on Modsim. The rst connects through to the instantiation fine as well a clk to clk_in_clk, but the value clk_out_clk ever changes. See below:

This makes me think the problem I'm having is with the PLL model created with Qsys.The model contained in the .vhd generated by Qsys is below:

-- PLL_4.vhd

-- Generated using ACDS version 13.0sp1 232 at 2016.02.09.16:46:16

library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;

entity PLL_4 is
port (
    clk_in_clk  : in  std_logic := '0'; --  clk_in.clk
    rst_reset   : in  std_logic := '0'; --     rst.reset
    clk_out_clk : out std_logic         -- clk_out.clk
);
end entity PLL_4;

architecture rtl of PLL_4 is
component PLL_4_altpll_0 is
    port (
        clk       : in  std_logic                     := 'X';             -- clk
        reset     : in  std_logic                     := 'X';             -- reset
        read      : in  std_logic                     := 'X';             -- read
        write     : in  std_logic                     := 'X';             -- write
        address   : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- address
        readdata  : out std_logic_vector(31 downto 0);                    -- readdata
        writedata : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
        c0        : out std_logic;                                        -- clk
        areset    : in  std_logic                     := 'X';             -- export
        locked    : out std_logic;                                        -- export
        phasedone : out std_logic                                         -- export
    );
end component PLL_4_altpll_0;

begin

altpll_0 : component PLL_4_altpll_0
    port map (
        clk       => clk_in_clk,  --       inclk_interface.clk
        reset     => rst_reset,   -- inclk_interface_reset.reset
        read      => open,        --             pll_slave.read
        write     => open,        --                      .write
        address   => open,        --                      .address
        readdata  => open,        --                      .readdata
        writedata => open,        --                      .writedata
        c0        => clk_out_clk, --                    c0.clk
        areset    => open,        --        areset_conduit.export
        locked    => open,        --        locked_conduit.export
        phasedone => open         --     phasedone_conduit.export
    );

end architecture rtl; -- of PLL_4

Can you add the internal signals to the waveform? Did you use the PLL wizard to generate it? Is there a blackbox warning in ModelSim? — Paebbels, Feb 09 '16 at 17:14
Yes I used a PLL wizard to generate a Avalon ALTPLL. There is no back box warning in modsim. If when you say add internal signals from the PLL, then I do not know where to find these that may be why I have the problem. — hoboBob, Feb 09 '16 at 18:02
There is a hierarchy view of your design. Currently, you selected the top-level (your testbench) where you can find your own signals. There should be a node called `CLK_25` as your PLL instance is named. Click on this sub-level and you'll see the signals of the generate wizard file (`PLL_4`). — Paebbels, Feb 09 '16 at 19:07
When I open the hierarchical view yes I see the PLL:CLK_25 but how does that help me to see the signal in modish? when I open this I can see the entity, component and architecture — hoboBob, Feb 09 '16 at 20:27
If you click on it (not double click), you can drag more signals into the waveform. The inner signals are needed to see, if for ex. the PLL does not leave the initial reset state. — Paebbels, Feb 09 '16 at 20:42
ahhhhhhhh Thank you, its the sim tab in modsim. hmmm the clk_out _clk of the PLL never changes state. I think this will take another post. — hoboBob, Feb 09 '16 at 21:42
Ah there is an Altera macro called `PLL_4_altpll_0` involved... Can you please add signals from the component, too. The inner most primitive should be called `ALTPLL`. This would be the physical PLL. The rest are just wrappers :). — Paebbels, Feb 09 '16 at 23:15
I think I might of found it. Some how Qsys is providing some files in VHDL and others in verilog. I've just found a load of.v extension files in the Hierarchy. — hoboBob, Feb 09 '16 at 23:16
How long did you simulate? PLLs need some time to lock and emit a clock -> several 100 cycles. A Virtex-5 DCM needs circa 160 us in simulation. After that time a clock is generated and then `locked` is asserted. — Paebbels, Feb 09 '16 at 23:18
I only tested for 6 periods top input 50Mhz expected output 25Mhz. Is it normal for Qsys to generate verilog files? The file PLL_4_altpll_0 is a .v extension. — hoboBob, Feb 09 '16 at 23:23
If I remember correctly, you can choose the generated language. People say the generated Verilog code has less errors... You need to simulate for a longer time :). — Paebbels, Feb 09 '16 at 23:26
I just ran the clk for 60 seconds with nothing. When a generated the PLL I remember selecting VHDL because it was set to verily by default. — hoboBob, Feb 09 '16 at 23:28

score 1 · Accepted Answer · answered Feb 10 '16 at 08:05

I could not directly simulate your VHDL code, because you didn't posted the code of PLL_4_altpll_0. Thus, I created an appropiate PLL with the MegaWizard Plugin Manager of Quartus-II. Anyway, if I directly simulate the PLL4 entity within ModelSim and apply a clock on signal clk as well as 1 to signal a, I get the same output as you: clk25 is undefined.

But if I use a separate testbench, it works as expected. You have to setup the testbench within Quartus II, menu Assignements -> Settings -> Simulation -> Compile test bench -> Test Benches -> New. Here is my testbench code. Applying a reset is optional, so I left it 0.

library ieee;
use ieee.std_logic_1164.all;

entity PLL4_tb is
end entity PLL4_tb;

architecture sim of PLL4_tb is

  -- component ports
  signal clk : std_logic := '1';
  signal a   : std_logic;
  signal rst : std_logic;
  signal x   : std_logic;

begin  -- architecture sim

  -- component instantiation
  DUT: entity work.PLL4
    port map (
      clk => clk,
      a   => a,
      rst => rst,
      x   => x);

  -- clock generation
  clk <= not clk after 10 ns;

  -- waveform generation
  WaveGen_Proc: process
  begin
    rst <= '0'; -- no reset required
    a   <= '1';
    wait;
  end process WaveGen_Proc;
end architecture sim;

And this is the simulation output:

VHDL - DE0 - QUARTUS II PLL not showing output in modsim

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