How can I achieve something similar to Xilinx' RLOC in Altera FPGAs?

Question

I have so far not found any way to do anything similar to Xilinx' RLOC constraints for Altera FPGAs.

Does anyone know a way to do this?

For example place two FFs in the same or adjacent LABs

If a specific design property is desired, like fast timing for a certain net, then you may be better off specifying this constrain directly, instead of relaying on getting such property through location constraining. In the end, location may tell nothing about actual routing between the instances, so you will have to constrain for the property you want anyway, in order to ensure post-placement check of this property. — Morten Zilmer, Aug 19 '14 at 19:48
I'm currently porting one of my Xilinx ISE projects to Vivado. I noticed that Xilinx supports xdc files, which are compatible to sdc files, which are supported by Altera and other vendors. I also noticed that *dc files are capable of describing constraints for submodules, so I think Xilinx relative location constraints (RLOC) can be translated into sdc files with a limited scope (Xilinx calls that SCOPE_TO_CELLS). So maybe you can find a Altera sdc-file User Guide which explains how to write scoped constraints and maybe there you can find a equivalent to relative locations ;) — Paebbels, Aug 20 '14 at 15:44

score 3 · Accepted Answer · answered Aug 20 '14 at 17:54

So to answer my own question, after some consultation with some Altera manuals and some trial and error, I found that this pretty much does what I want.

module synchronizer (input wire dat_i,

                     input wire out_clk,
                     output wire dat_o);

   (* altera_attribute = "-name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2; -name SYNCHRONIZER_IDENTIFICATION \"FORCED IF ASYNCHRONOUS\"" *)
   logic [1:0]                   out_sync_reg;

   always_ff@(posedge out_clk) begin
      out_sync_reg <= {out_sync_reg[0],dat_i};
   end

   assign dat_o = out_sync_reg[1];

endmodule

I tested this by setting global synchronizer detection to off and observed that TimeQuest found and analysed the correct paths for metastability.

This works well even when dat_i is latched by clk_a and out_clk is driven by clk_b and where the two clocks are set as:

set_clock_groups -asynchronous -group {clk_a}
set_clock_groups -asynchronous -group {clk_b}

Thus creating false paths between all connections from registers clocked by clk_a to registers clocked by clk_b

set_max/min_delay wont work since it is ignored (as stated by Altera) if the the two clocks are in different asynchronous clock groups.

You'd be better off embedding the false path constraint too: `(* altera_attribute = "-name SDC_STATEMENT \"set_false_path -to [get_registers {*synchronizer*out_sync_reg[0]}]\"" *)`. Setting a global false path between two clock domains generally isn't advisable as it can mask mistakes. See [this answer](http://electronics.stackexchange.com/questions/122509/clock-domain-crossing-timing-constraints-for-altera/123101#123101). — Chiggs, Aug 21 '14 at 08:22

score 1 · Answer 2 · edited Apr 13 '17 at 12:32

Altera do not support RLOC style constraints. Apparently this is something to do with the underlying physical architecture. I believe they over-provision ALMs and fuse out columns during chip test to improve yield, therefore relative locations constraints won't translate as expected to a given physical device.

If you are worried about a synchroniser chain placement, you can enable synchroniser chain detection using SYNCHRONIZATION_REGISTER_CHAIN_LENGTH and SYNCHRONIZER_IDENTIFICATION QSF settings (see also this answer).

If you just want to ensure particular timing properties then use set_max_delay and set_min_delay timing constraints on your path.

How can I achieve something similar to Xilinx' RLOC in Altera FPGAs?

2 Answers2