ModelSim does not compile overloaded functions and undefined range types

Question

I'm running ModelSim 10.3d, and I have this code in a package:

package core_params_types is
    type array_1d_logic is array (natural range <>) of std_logic;
type array_1d_logic_vector is array (natural range <>) of std_logic_vector (natural range <>);
type array_2d_logic is array (natural range <>, natural range <>) of std_logic;
type array_2d_logic_vector is array (natural range <>, natural range <>) of std_logic_vector (natural range <>);

function or_reduce_2d_logic(a : array_2d_logic; i : integer) return std_logic;
function or_reduce_2d_logic_vector(a : array_2d_logic_vector; i : integer) return std_logic_vector;

function bitwise_cmp(a : std_logic_vector; b : std_logic_vector) return std_logic;
function bitwise_cmp(a : std_logic; b : std_logic) return std_logic;

function full_adder(a : std_logic_vector; b : std_logic_vector; ci : std_logic) return std_logic_vector;

function sign_extend(a : std_logic_vector; b : integer) return std_logic_vector;
function sign_extend(a : std_logic; b : integer) return std_logic_vector;
function logic_extend(a : std_logic_vector; b : integer) return std_logic_vector;
function logic_extend(a : std_logic; b : integer) return std_logic_vector;

ModelSim spits the following errors:

-- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package MATH_REAL
# -- Loading package ATTRIBUTES
# -- Loading package std_logic_misc
# -- Compiling package core_params_types
# ** Error: core_params_types.vhd(40): near "<>": syntax error
# ** Error: core_params_types.vhd(42): near "<>": syntax error
# ** Error: core_params_types.vhd(45): (vcom-1136) Unknown identifier "array_2d_logic_vector".
# ** Error: core_params_types.vhd(48): (vcom-1295) Function "bitwise_cmp" has already been defined in this region.
# ** =====> Prior declaration of "bitwise_cmp" is at core_params_types.vhd(47).
# ** Error: core_params_types.vhd(53): (vcom-1295) Function "sign_extend" has already been defined in this region.
# ** =====> Prior declaration of "sign_extend" is at core_params_types.vhd(52).
# ** Error: core_params_types.vhd(55): (vcom-1295) Function "logic_extend" has already been defined in this region.
# ** =====> Prior declaration of "logic_extend" is at core_params_types.vhd(54).
# ** Error: core_params_types.vhd(310): VHDL Compiler exiting

The .do file contains the following commands:

transcript on
if {[file exists rtl_work]} {
    vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vcom -2008 -work work {core_params_types.vhd}
vcom -2008 -work work {alu.vhd}

vcom -2008 -work work {tb_alu.vhd}
vcom -2008 -work work {alu.vhd}

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L rtl_work -L work -voptargs="+acc"  tb_alu

add wave *
view structure
view signals
run -all

I run the ModelSim simulation from Quartus, which compiles the code without errors, and generates a circuit. ModelSim says that the functions are already defined. That is correct, but they have different types, so they should be overloaded. And also ModelSim does not understand the declaration of the array types.

Answer 1

A type declaration

type array_1d_logic_vector is array (natural range <>) of std_logic_vector (natural range <>);

is not valid. You do not declare the index type of the element type. Instead try:

type array_1d_logic_vector is array (natural range <>) of std_logic_vector;

You constrain the element subtype in an object declaration for example:

variable foo: array_1d_logic_vector(0 to 1)(7 downto 0);

Where the element subtype constraint is 7 downto 0 and the array constraint is 0 to 1.

See IEEE Std 1076-2008 5.3.2 Array types, 5.3.2.1 General paragraph 6:

An unbounded array definition in which the element subtype indication denotes either an unconstrained composite subtype or a subtype that is not a composite subtype defines an array type and a name denoting that type. For each object that has the array type, the number of indices, the type and position of each index, and the subtype of the elements are as in the type definition. The index subtype for a given index position is, by definition, the subtype denoted by the type mark of the corresponding index subtype definition. The values of the left and right bounds of each index range are not defined, but shall belong to the corresponding index subtype; similarly, the direction of each index range is not defined. The symbol <> (called a box) in an index subtype definition stands for an undefined range (different objects of the type need not have the same bounds and direction).

There is a code example found in 5.3.2.1 (toward the end).

And if the second form looks easy to mess up, it is. You can declare objects of the same type with elements that have different subtype constraints and are incompatible when their lengths differ.

Without seeing the log file output for any synthesis operations using the original successful synthesis would not be compliant to the VHDL standard.

Without going through everything with a fine tooth comb your test case package declaration doesn't match the line numbers given in example code. It seems like you are re-declaring functions in the package body (noting the line number 310). Try removing the duplicate function declarations.

(You could also provide an actual Minimal, Complete, and Verifiable example, it'd do wonders for telling exactly what's going on).