Is N-1 the largest term which could be used for Generic in VHDL

Question

I am new to VHDL and I wanted to ask that what generic term could I use If i wanted to write any size of input vector which could be developed?

GENERIC (n1 : integer); 
x:IN BIT_VECTOR(n1-1 downto 0);

Is that a correct example?

Answer 1

According to the " Paebbels" comment I edit this answer :

Every time you want to synthesize your code, synthesis tool should know about the size of parameters you used, Otherwise what exactly you want to synthesize ?!!! (what hardware ?!)

If you want to synthesize your top module code which contains a generic parameter in it's own entity, you can assign it with a default value such as the following code :

ENTITY ... IS
    GENERIC(n1 : INTEGER := 8);
    PORT(
         -- use generic parameter
    );
END ENTITY;

Also you can use the generic parameter inside architecture ( size of signals, index of loops, ... ).

Answer 2

Your generic has no default value visible.

Your declaration for x is incomplete. It appears to be an entity declarative item with a mode while you don't have a port declaration.

This VHDL code is syntactically and semantically valid:

entity foo is
    generic ( n1:   integer);
    port (
        x: in   bit_vector(n1-1 downto 0)
    );
end entity;

architecture fum of foo is

begin

end architecture;

It will analyze. It can't be elaborated without the value of n1 being known:

entity foo_tb is
    constant N_1: integer := 4;
end entity;

architecture fum of foo_tb is
    signal x:  bit_vector (N_1-1 downto 0);
begin
DUT:
    entity work.foo
    generic map (n1 => N_1)
    port map ( x => x);
end architecture;

Entity foo by itself can't be the top level of an elaborated model because n1 isn't defined for elaboration.

Entity foo_tb can be elaborated, it uses the constant N_1 to supply a value to n1.

foo_tb can even be simulated, but it will exit immediately because there are no pending signal assignments after initialization.

Neither foo nor foo_tb can be synthesize. foo_tb because it has no ports and any logic in it's design hierarchy would be optimized away as unused. foo because it only has an output and is at best a constant.

If foo had multiple ports, with outputs depending on inputs it would be eligible for synthesis or simulation as long as the generic was defined for elaboration.

(And the moral here is to use a Minimal, Complete, and Verifiable example so someone doesn't have to wave their hands around it's shortcomings).

Answer 3

You can use every term, as far as it's result does not exceed the BIT_VECTORS's array range.

BIT_VECTOR definition: type BIT_VECTOR is array (NATURAL range <>) of BIT;
So your term can have results from 0 to 2**32 - 1

Term examples:

• 4*n1 - 1 downto 0
• n1/4 + 8 downto 0
• log2ceilnz(n1) - 1 downto 0
• 2**n1 - 1 downto 0