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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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What does `addi a0, zero, 2` mean in pseudocode?

What does addi a0, zero, 2 mean in pseudocode? Is it a0=a0+2?? I am not sure because we do not have explicit register in this instruction to tell us where goes our result.
Tony Stark
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I can't find resources of this version of Assembly online

So I'm taking a Systems - Hardware class and in this class we're also learning about Assembly. Our professor gave us a simulator and it's documentation but I can't find anything else about this version of Assembly outside the documentation. Here…
idkrlly
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Please explain the issue of sensitive instructions in Virtualization and how it is resolved

In virtualization,is sensitive instructions an issue because it probably gets executed in non-privileged mode without getting trapped or raising an interrupt? In hardware-assisted virtualization, is the Intel-VT, AMD Pacifica solving the problem by…
James Dsouza
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What instruction set does the intel i7- 8705G use?

I need to convert some code to the ISA of the intel i7-8705G but i do not know which version of the x86-64 ISA it uses. I want to use godbolt here and select the ISA from the drop down list but there are several versions of the x86-64. Which one is…
Greg
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X86 instruction format according to SDM

I see the following instruction format description of ADD according to X86 SDM manual. This is somehow different from what I have seen before in 8086 instruction format. There we have OPCODE | DIRECTION | WIDTH MOD | REG | R/M 6 …
mahmood
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How to write a very simple instruction set with the following requirements?

I am very new to coding. I am trying to understand how to write an instruction set, that is very simple. the requirement are these basics: read, write, add, subtract,enable loop/conditional operation. I was trying to find example codes, online…
Alexandra
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with this Fibonacci sequence question with instruction sets used to make a assembly code

This is a Fibonacci sequence that I recently attempted to turn into a assembly code through the use of instruction set. I am not sure how to go about testing it and was wondering could confirm if I got this right and if not where I went wrong. Also…
mickraj122
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Are more opcodes represented using the R instruction format?

If the opcode for R-format instruction can be all 0s and the six least significant bits can be used instead, does this mean that more opcodes can be represented with the R-format? Since the other instruction formats do not have the funct…
Tina
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My interpreter language doesn't seem to recognise the "+" symbol and is returning errors. How have I gone wrong in my code?

I have written an interpreter that takes a String as an instruction set. This instruction set declares a set of variables and returns one of them. An example instruction set would be: A = 2 B = 8 C = A + B C This is supposed to return the variable…
user10745934
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How does a CPU knows how to interpret instruction?

MIPS ISA has 3 instruction formats: R, I, J. Each format being decode in the different way. (R type - opcode | rs | rt | rd | shamt | funct) etc. And we have some instruction - 10111010010000110011010101101110 How does CPU knows in which the way…
Vitaliy
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Why doesn't code branch at BEQ after MOVS

Id really appreciate if somebody could help me. Why doesn't code branch on the first reading of BEQ, if comparing r2 with r2. Apparently the final value in r0 is 0X0000001B. Thank you so much, im very confused and frustrated running this over and…
mangokitty
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How to interpret BLO in this example

In this example im trying to figure out what the BLO is comparing. I know it branches if the carry flag is not set. Is it comparing r1 with old r1 (the instruction above it?) As the code doesn't branch at BGE. Thanks so much. …
mangokitty
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Write to flash PIC18f4550 datasheet example

In the datasheet of PIC18F4550 the example to write to flash program memory is the following: MOVLW D'64’ ; number of bytes in erase block MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH ; point to…
esencia
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How to get the ISA06 Interchange Sender ID of an FTP transfer in debian linux

I have been following a trail of breadcrumbs for a couple days now. My company is needing a simple API/EDI built that can communicate with a bunch of different marketplaces. One of them requires I give them the ISA Interchange Sender ID to even make…
shamelessApathy
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opcode of %ebx register

I wrote the following assembly program to get the opcode of various registers: .section .text .globl _start _start: add $1,%eax add $1,%ebx …
builder-7000
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